Abstract: A photonic device includes an optical coupler, a photodetector, a waveguide structure, a metal-dielectric stack, a contact, an interlayer dielectric layer, and a protection layer. The optical coupler, the photodetector, and the waveguide structure are over a substrate. The waveguide structure is laterally connected to the optical couple. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler, the photodetector, and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The contact connects the photodetector to the metal-dielectric stack. The interlayer dielectric layer is below the metal-dielectric stack and surrounds the contact. The protection layer lines the hole of the metal-dielectric stack. A bottom surface of the protection layer is lower than a top surface of the contact.

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Abstract: A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Abstract: A power supply phase doubling system includes a pulse width modulation (PWM) controller and first and second phase doubling chips. The PWM controller outputs a PWM signal. The first phase doubling chip is operated at a power supply voltage and has a first PWM output pin to generate a first control signal and a second control signal according to the PWM signal, and generates a first output signal according to the first control signal. The second phase doubling chip is operated at the power supply voltage, has a second PWM output pin, and is configured to generate a second output signal according to the second control signal. The first and second phase doubling chips are respectively switched between a master mode and a slave mode according to a voltage level of the first PWM output pin and a voltage level of the second PWM output pin.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: A photonic device includes an optical coupler, a waveguide structure, a metal-dielectric stack, and a protection layer. The optical coupler is over a semiconductor substrate. The waveguide structure is over the semiconductor substrate and laterally connected to the optical coupler. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The protection layer lines the hole of the metal-dielectric stack.

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

Abstract: A driving circuit includes a cross coupled circuit, a first conducting device, a second conducting device, a first switching device, a second switching device, a first selecting device and a second selecting device. The first conducting device is connected between a first node and a second node. The second conducting device is connected between a third node and a fourth node. The cross coupled circuit receives a first supply voltage and is connected with the first node and the second node. The first switching device is connected between the second node and a fifth node. The second switching device is connected between the fourth node and a sixth node. The first and second selecting devices are respectively connected with the fifth node and the sixth node. Each of the first and second selecting devices receives a second supply voltage and a third supply voltage.

Abstract: A method of forming a CMP pad includes providing a solution of a block copolymer (BCP), where the BCP includes a first segment and a second segment connected to the first segment, the second segment being different from the first segment in composition. The method further includes processing the BCP to form a polymer network having a first phase and a second phase embedded in the first phase, where the first phase includes the first segment and the second phase includes the second segment, and subsequently removing the second phase from the polymer network, thereby forming a polymer film that includes a network of pores embedded in the first phase. Thereafter, the method proceeds to combining the CMP top pad and a CMP sub-pad to form a CMP pad, where the CMP top pad is configured to engage with a workpiece during a CMP process.

Abstract: A semiconductor package structure is provided. The structure includes a package substrate having a first surface and a second surface opposite to the first surface and including a ground layer embedded therein. A semiconductor die is formed on the first surface of the package substrate and an antenna pattern layer is formed on the second surface of the package substrate and electrically coupled to the semiconductor die. The structure also includes a first connector and a second connector formed on the second surface of the package substrate and arranged adjacent to the antenna pattern layer. The first connector is electrically coupled to the semiconductor die and electrically isolated to the ground layer, and the second connector is electrically coupled to the ground layer. A wireless communication device including the semiconductor package structure is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.

Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.