Patents by Inventor Chen Liang

Chen Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190363165
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Inventors: TA-YUAN KUNG, RUEY-HSIN LIU, CHEN-LIANG CHU, CHIH-WEN YAO, MING-TA LEI
  • Publication number: 20190345033
    Abstract: A high-purity chlorine dioxide gas may use hydrogen peroxide as a reducing agent and may use horizontal generator, evaporation crystallizer, dryer and other devices to produce chlorine dioxide gas (product) and sodium sulfate (by-product). Compared to the conventional chlorine dioxide preparation system, the chlorine dioxide reaction and the sodium sulfate crystallization are performed in two processes. These processes are relatively separate and independent, and continuously produce chlorine dioxide gas with high purity and low moisture content while the by-product salt cake is evaporated, crystallized, filtered and dried, thereby producing sodium sulfate, without generating solid and liquid waste.
    Type: Application
    Filed: November 6, 2018
    Publication date: November 14, 2019
    Inventors: Shuangfei WANG, Chengrong QIN, Shuangxi NIE, Xueping SONG, Chen LIANG, Xinliang LIU, Zhiwei WANG, HongXiang ZHU
  • Publication number: 20190339989
    Abstract: The devices, systems, and methods described herein enable automatically configuring an electronic device using artificial intelligence (AI). The devices, systems, and methods enable accessing telemetry data representing device usage data, inputting the accessed telemetry data into machine learning models that are matched to device metadata, and determining notifications to publish to components of the electronic device. The notifications represent events predicted to occur on the electronic device. The notifications are published to the components of the electronic device such that the electronic device is configured according to the published notifications. The determined notifications enable the identification of optimal settings for the electronic device based on the usage pattern of the device and enable components of the electronic device to preemptively take action on events which are predicted to occur in the future.
    Type: Application
    Filed: May 31, 2018
    Publication date: November 7, 2019
    Inventors: Chen LIANG, Bryston M. NITTA, Shayak LAHIRI, Adrian Francisco Teran GUAJARDO
  • Patent number: 10468817
    Abstract: A housing device with slidable engagement includes a housing body, a fitting, and a sliding buckle. The housing body includes an opening side and a lateral adjacent to the opening side. The lateral has a through hole, and an inner surface of the lateral is provided with a guide structure. The fitting is inserted into the housing body through the through hole. The sliding buckle is slidably assembled on the guide structure. The sliding buckle includes two clamping arms, and the two clamping arms correspondingly clamp to an outside of the fitting.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 5, 2019
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Chen-Liang Lee, Yu-Cheng Liu
  • Publication number: 20190334280
    Abstract: A housing device with slidable engagement includes a housing body, a fitting, and a sliding buckle. The housing body includes an opening side and a lateral adjacent to the opening side. The lateral has a through hole, and an inner surface of the lateral is provided with a guide structure. The fitting is inserted into the housing body through the through hole. The sliding buckle is slidably assembled on the guide structure. The sliding buckle includes two clamping arms, and the two clamping arms correspondingly clamp to an outside of the fitting.
    Type: Application
    Filed: October 1, 2018
    Publication date: October 31, 2019
    Inventors: Chen-Liang Lee, Yu-Cheng Liu
  • Publication number: 20190237485
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 10290644
    Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignee: Powerchip Technology Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Publication number: 20190130251
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a system output from a system input using a neural network system comprising an encoder neural network configured to, for each of a plurality of encoder time steps, receive an input sequence comprising a respective question token, and process the question token at the encoder time step to generate an encoded representation of the question token, and a decoder neural network configured to, for each of a plurality of decoder time steps, receive a decoder input, and process the decoder input and a preceding decoder hidden state to generate an updated decoder hidden state.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 2, 2019
    Inventors: Ni Lao, Chen Liang, Quoc V. Le, John Blitzer
  • Patent number: 10276596
    Abstract: Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 10266406
    Abstract: A high-purity chlorine dioxide gas may use hydrogen peroxide as a reducing agent and may use horizontal generator, evaporation crystallizer, dryer and other devices to produce chlorine dioxide gas (product) and sodium sulfate (by-product). Compared to the conventional chlorine dioxide preparation system, the chlorine dioxide reaction and the sodium sulfate crystallization are performed in two processes. These processes are relatively separate and independent, and continuously produce chlorine dioxide gas with high purity and low moisture content while the by-product salt cake is evaporated, crystallized, filtered and dried, thereby producing sodium sulfate, without generating solid and liquid waste.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 23, 2019
    Inventors: Shuangfei Wang, Chengrong Qin, Shuangxi Nie, Xueping Song, Chen Liang, Xinliang Liu, Zhiwei Wang, HongXiang Zhu
  • Publication number: 20190018729
    Abstract: Examples described herein generally relate to device analytics. Specifically, the present disclosure provides telemetry-based analytics to identify and remediate top end-user impacting issues. For example, a device may detect an anomaly associated with an application program at the computing device based on a detection parameter. Further, the device may automatically identify at least one remediation action associated with the detected anomaly. The device may also determine whether application of the at least one remediation action to the detected anomaly satisfies a remediation threshold. Additionally, the device may transmit the at least one remediation action to the computing device in accordance with a determination that the application of the at least one remediation action to the detected anomaly satisfies the remediation threshold.
    Type: Application
    Filed: March 8, 2018
    Publication date: January 17, 2019
    Inventors: Marc SHEPARD, Marc-Andrea KLIMASCHEWSKI, Chen LIANG, Ramasubramanian SHASTRI, Hung M. DANG, Bryston M. NITTA, Oana S. NICA
  • Patent number: 10164037
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chih-Wen Albert Yao, Fu-Jier Fan, Chen-Liang Chu, Ta-Yuan Kung, Yi-Huan Chen, Yu-Bin Zhao, Ming-Ta Lei, Li-Hsuan Yeh
  • Patent number: 10145017
    Abstract: An efficient electrolysis system for sodium chlorate production may include round or oval cells, reactors, a product pump transfer, a buffer tank, a circulation pump, and explosive clad plate, all of which are connected by way of pipelines. Inlet and the outlet of each cell are separately connected with the reactor via titanium pipes, allowing the electrolyte to recirculate naturally between the cells and the reactors. The outlet of every cell is conical while each reactor includes a standard electrolytic unit with three to eight cells. The electrolytic units are modularly identical and symmetrically linked to the buffer tank. Within each unit, adjacent cells are connected with the explosive clad plates. The buffer tank may be divided into two parts—part A and part B—with part A connecting with the overflow port of the reactor via pipeline, and the part B connecting with the reactor via the circulation pump.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 4, 2018
    Inventors: Shuangfei Wang, Chengrong Qin, Xusheng Li, Chen Liang, Xinliang Liu, Zhiwei Wang
  • Publication number: 20180337128
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20180328874
    Abstract: A nitrogen oxide gas sensor based on sulfur-doped graphene and a preparation method therefor. The method comprises the following steps: 1) providing graphene and a micro heater platform substrate, and transferring the graphene onto the micro heater platform substrate; 2) putting the micro heater platform substrate covered with the graphene into a chemical vapor deposition reaction furnace; 3) performing gas feeding and exhausting treatment to the reaction furnace by using inert gas; 4) simultaneously feeding inert gas and hydrogen gas into the reaction furnace at a first temperature; 5) feeding inert gas, hydrogen gas and sulfur source gas into the reaction furnace at a second temperature for reaction to perform sulfur doping to the graphene (21); and 6) stopping feeding the sulfur source gas, and performing cooling in a hydrogen gas and insert gas shielding atmosphere.
    Type: Application
    Filed: January 6, 2016
    Publication date: November 15, 2018
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: TIE LI, LIANFENG GUO, CHEN LIANG, YUELIN WANG
  • Patent number: 10106900
    Abstract: An efficient electrolysis system for sodium chlorate production may include round or oval cells, reactors, a product pump transfer, a buffer tank, a circulation pump, and explosive clad plate, all of which are connected by way of pipelines. Inlet and the outlet of each cell are separately connected with the reactor via titanium pipes, allowing the electrolyte to recirculate naturally between the cells and the reactors. The outlet of every cell is conical while each reactor includes a standard electrolytic unit with three to eight cells. The electrolytic units are modularly identical and symmetrically linked to the buffer tank. Within each unit, adjacent cells are connected with the explosive clad plates. The buffer tank may be divided into two parts—part A and part B—with part A connecting with the overflow port of the reactor via pipeline, and the part B connecting with the reactor via the circulation pump.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 23, 2018
    Inventors: Shuangfei Wang, Chengrong Qin, Xusheng Li, Chen Liang, Xinliang Liu, Zhiwei Wang
  • Publication number: 20180300180
    Abstract: Examples described herein generally relate to device analytics. Specifically, the present disclosure provides resource deployment at an organization including one or more devices. The present disclosure provides for receiving telemetry data from the one or more devices associated with the organization. The present disclosure further provides for generating a set of deployment rings for the deployment of the software resource at the one or more devices of the organization. Additionally, the present disclosure provides for deploying the software resource within the organization based on the set of deployment rings.
    Type: Application
    Filed: March 8, 2018
    Publication date: October 18, 2018
    Inventors: Marc SHEPARD, Marc-Andrea KLIMASCHEWSKI, Chen LIANG, Ramasubramanian SHASTRI, Hung Minh DANG, Bryston Mitsuo NITTA, Oana Silvia NICA
  • Publication number: 20180286877
    Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 4, 2018
    Applicant: Powerchip Technology Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Publication number: 20180286960
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Ker-Hsiao HUO, Kong-Beng THEI, Chih-Wen Albert YAO, Fu-Jier FAN, Chen-Liang CHU, Ta-Yuan KUNG, Yi-Huan CHEN, Yu-Bin ZHAO, Ming-Ta LEI, Li-Hsuan YEH
  • Publication number: 20180282883
    Abstract: An efficient electrolysis system for sodium chlorate production may include round or oval cells, reactors, a product pump transfer, a buffer tank, a circulation pump, and explosive clad plate, all of which are connected by way of pipelines. Inlet and the outlet of each cell are separately connected with the reactor via titanium pipes, allowing the electrolyte to recirculate naturally between the cells and the reactors. The outlet of every cell is conical while each reactor includes a standard electrolytic unit with three to eight cells. The electrolytic units are modularly identical and symmetrically linked to the buffer tank. Within each unit, adjacent cells are connected with the explosive clad plates. The buffer tank may be divided into two parts—part A and part B—with part A connecting with the overflow port of the reactor via pipeline, and the part B connecting with the reactor via the circulation pump.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Shuangfei Wang, Chengrong Qin, Xusheng Li, Chen Liang, Xinliang Liu, Zhiwei Wang