Patents by Inventor Chen Lin

Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974302
    Abstract: A method and a User Equipment (UE) for beam operations are provided. The method includes monitoring at least one of a plurality of Control Resource Sets (CORESETs) configured for the UE within an active Bandwidth Part (BWP) of a serving cell in a time slot; and applying a first Quasi Co-Location (QCL) assumption of a first CORESET of a set of one or more of the monitored at least one of the plurality of CORESETs to receive a Downlink (DL) Reference Signal (RS), wherein the first CORESET is associated with a monitored search space configured with a lowest CORESET Identity (ID) among the set of one or more of the monitored at least one of the plurality of CORESETs.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: April 30, 2024
    Assignee: Hannibal IP LLC
    Inventors: Chien-Chun Cheng, Tsung-Hua Tsai, Yu-Hsin Cheng, Wan-Chen Lin
  • Patent number: 11972562
    Abstract: A method for determining a plant growth curve includes obtaining color images and depth images of a plant to be detected at different time points, performing alignment processing on each color image and each depth image to obtain an alignment image, detecting the color image through a pre-trained target detection model to obtain a target bounding box, calculating an area ratio of the target bounding box in the color image, determining a depth value of all pixel points in the target boundary frame according to the aligned image, performing denoising processing on each depth value to obtain a target depth value, generating a first growth curve of the plant to be detected according to the target depth values and corresponding time points, and generating a second growth curve of the plant to be detected according to the area ratios and the corresponding time points.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 30, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Te Lu, Chin-Pin Kuo, Tzu-Chen Lin
  • Patent number: 11970793
    Abstract: A fabric of a cup body of a brassiere includes an inner textile layer, an outer textile layer and a middle textile layer. A first weaving region and a second weaving region of the outer textile layer respectively include a plurality of composite yarns. Each of the composite yarns includes a first yarn and a second yarn. A melting point of the first yarn is lower than a melting point of the second yarn, and an offset rate of the second yarn relative to the first yarn is from 5% to 300%. A content of the composite yarns in the first weaving region is greater than that in the second weaving region. A content of the composite yarns in a third weaving region of the outer textile layer is less than that in the second weaving region. The first weaving region is at a lifting area of the cup body.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 30, 2024
    Assignee: MACKENT GROUP CO., LTD.
    Inventors: Yi-Chen Lin, Po-Jen Shih
  • Patent number: 11972799
    Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: April 30, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Chia-Hung Lin, Jun-Yao Huang
  • Patent number: 11971368
    Abstract: The present disclosure provides a determination method, an elimination method and an apparatus for an electron microscope aberration. The determination method comprises: training a neural network for image recognition using a plurality of electron microscope simulation images to obtain an electron microscope image recognition model; recognizing an electron microscope image of an experimental sample using the electron microscope image recognition model to obtain the electron microscope simulation image corresponding to the electron microscope image of the experimental sample; and obtaining the corresponding set aberration as an imaging aberration of the electron microscope image of the experimental sample according to the electron microscope simulation image corresponding to the electron microscope image of the experimental sample.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: April 30, 2024
    Assignee: SOUTH CHINA AGRICULTURAL UNIVERSITY
    Inventors: Fang Lin, Qi Zhang, Chen Wang
  • Patent number: 11974311
    Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: April 30, 2024
    Assignee: Hannibal IP LLC
    Inventors: Wan-Chen Lin, Yu-Hsin Cheng, Heng-Li Chin, Hsin-Hsi Tsai
  • Publication number: 20240134163
    Abstract: An image capturing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, and a sixth lens element. The first lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The second and third lens elements have refractive power. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof. The sixth lens element with refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The image capturing lens assembly has a total of six lens elements with refractive power.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Chen LIN, Wei-Yu CHEN
  • Publication number: 20240138138
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240136246
    Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Publication number: 20240138139
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 25, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240138152
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
  • Publication number: 20240137400
    Abstract: A media item to be provided to users of a platform is identified. The media item is associated with a media class of one or more media classes. An indication of the media item is provided as input to a machine learning model trained based on historical encoding data to predict, for a given media item, a set of encoder parameter settings that satisfy a performance criterion in view of a respective media class of the given media item. The historical encoding data includes a prior set of encoder parameter settings that satisfied the performance criterion with respect to a prior media item associated with the respective class. Encoder parameter settings that satisfy the performance criterion in view of the media class is determined based on an output of the model. The media item is caused to be encoded using the determined encoder parameter settings.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching Yin Derek Pang, Kyrah Felder, Akshay Gadde, Paul Wilkins, Cheng Chen, Yao-Chung Lin
  • Patent number: 11965217
    Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
  • Patent number: 11966832
    Abstract: A method includes receiving a first data set comprising embeddings of first and second types, generating a fixed adjacency matrix from the first dataset, and applying a first stochastic binary mask to the fixed adjacency matrix to obtain a first subgraph of the fixed adjacency matrix. The method also includes processing the first subgraph through a first layer of a graph convolutional network (GCN) to obtain a first embedding matrix, and applying a second stochastic binary mask to the fixed adjacency matrix to obtain a second subgraph of the fixed adjacency matrix. The method includes processing the first embedding matrix and the second subgraph through a second layer of the GCN to obtain a second embedding matrix, and then determining a plurality of gradients of a loss function, and modifying the first stochastic binary mask and the second stochastic binary mask using at least one of the plurality of gradients.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: April 23, 2024
    Assignee: Visa International Service Association
    Inventors: Huiyuan Chen, Yu-San Lin, Lan Wang, Michael Yeh, Fei Wang, Hao Yang
  • Patent number: 11967547
    Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11967272
    Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 23, 2024
    Assignees: AUO Corporation, National Cheng-Kung University
    Inventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
  • Patent number: 11967582
    Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11968659
    Abstract: The present disclosure provides a method of scheduling for a UE. The method includes dividing M UEs into N groups, wherein a distance metric between each UE in a group and the center of the group does not exceed a first predetermined threshold, where M and N are positive integers; pairing the N groups, wherein a distance metric between centers of the two paired groups is greater than a second predetermined threshold; and in a case where there is a group paired with a group to which a first UE for which scheduling is to be performed belongs, scheduling transmissions in different directions respectively for the first UE and the second UE from the paired group on the same time-frequency resource. The present disclosure also provides a signal transmission method, a base station, a UE and a computer readable medium.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chuang Zhang, Di Su, Peng Lin, Chen Qian, Bin Yu
  • Patent number: D1024640
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 30, 2024
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Fang-Cheng Su, Ci-Bin Huang, Ching-Fu Chiu, Shu-Chen Lin
  • Patent number: D1025074
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 30, 2024
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Chiung-Wei Lin, Yi-Chen Chen