Abstract: A cold plate is provided and includes: a housing disposed with a chamber; a base combined with the housing to form a working space separated from the chamber but connected with the chamber through an interconnecting structure to allow a working medium to flow within the chamber and the working space; a heat transfer structure disposed on the inner side of the base; and a pump disposed within the working space to drive the working medium in the working space. As such, the cold plate can provide better heat dissipation performance.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

Abstract: A modulation device including a plurality of electronic elements, at least one first signal line and a first driving circuit is provided. The at least one first signal line is respectively electrically connected to at least one of the electronic elements. The first driving circuit is electrically connected to the at least one first signal line. The first driving circuit provides a first signal to at least one of the at least one first signal line. The first signal includes a first pulse. The first pulse includes a first section and a second section closely adjacent to the first section.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the plat

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.

Abstract: A method for preparing protein nanoparticle microspheres includes: dispersing a protein powder in water, adjusting a pH of a solution of the protein powder to between 10.0 and 12.0, stirring, centrifuging, and collecting a first upper dispersion; adjusting the first upper dispersion to be neutral using a cation exchange resin, centrifuging, to yield a protein nanoparticle dispersion; adding eugenol to the protein nanoparticle dispersion, stirring, centrifuging, and removing a precipitant, to yield a core-shell nanoprotein dispersion comprising a eugenol core and a protein shell; and adding the core-shell nanoprotein dispersion to ultrapure water, dialyzing, centrifuging, collecting a second upper dispersion, freeze-drying the second upper dispersion, to yield protein nanoparticle microspheres.

Abstract: Systems and techniques are described herein for modifying the scale and/or position of objects in images. For instance, a system can obtain a two-dimensional (2D) input image from a camera and a three-dimensional (3D) representation of the 2D input image. The system can further determine a first portion of the 3D representation of the 2D input image corresponding to a target object in the 2D input image. The system can adjust a pose of the first portion of the 3D representation of the 2D input image corresponding to the target object. The system can further generate a 2D output image having a modified version of the target object based on the adjusted pose of the first portion of the 3D representation of the 2D input image corresponding to the target object to be output on a display.

Abstract: An optical system is provided. The optical system includes a first movable portion, a fixed portion, a first driving assembly, and a first sensing assembly. The first movable portion is used for connecting to an optical assembly having a main axis. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The first sensing assembly is used for sensing the movement of the first movable portion relative to the fixed portion.

Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.

Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

Abstract: Optical devices and methods of manufacture are presented in which an opening is formed within a first semiconductor device and then bonded to other optical devices. A laser die or other fill material may be used to refill the opening. The first semiconductor device is then electrically connected to an optical interposer.

Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.

Abstract: A method for identifying a set of optimized financing programs to provide to a merchant may include receiving historical loan application data defining historical parameters associated with corresponding historical loan applications, replacing at least a portion of the historical parameters of the historical loan application data with new parameters associated with different loan terms to define a simulated loan data set defining simulated financing programs, determining a selection probability score for each of the simulated financing programs, the selection probability score indicating a likelihood of customer selection of each respective one of the simulated financing programs, determining a cash flow rating for each of the simulated financing programs, the cash flow rating estimating cash flow over time for the each respective one of the simulated financing programs, determining a valuation score based on the selection probability score and the cash flow rating of the each respective one of the simulated

Abstract: A method includes forming an optical engine, which includes a photonic die. The photonic die further includes a grating coupler. The method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. The optical fiber extends into the groove. The fiber platform further includes a reflector. The fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.

Abstract: Disclosed herein are electronic devices that include arrays of dual function light transmit and receive pixels. The pixels of such arrays include a photodetector (PD) structure and a vertical-cavity, surface-emitting laser (VCSEL) diode, both formed in a common stack of epitaxial semiconductor layers. The pixels of the array may be configured by a controller or processor to function either as a light emitter by biasing the VCSEL diode, or as a light detector or receiver by a different bias applied to the PD structure, and this functionality may be altered in time. The array of dual function pixels may be positioned interior to an optical display of an electronic device, in some cases to provide depth sensing or autofocus. The array of pixels may be registered with a camera of an electronic device, such as to provide depth sensing or autofocus.

Abstract: One embodiment of a method for generating representations of scenes includes assigning each image included in a set of images of a scene to one or more clusters of images based on a camera pose associated with the image, and performing one or more operations to generate, for each cluster included in the one or more clusters, a corresponding three-dimensional (3D) representation of the scene based on one or more images assigned to the cluster.

Abstract: A fan module includes a hub, a plurality of fan blades, and a ring frame. The hub is configured to rotate about a central axis. The plurality of fan blades surround the hub. Each of the plurality of fan blades includes a first end portion connected to the hub and a second end portion opposite to the first end portion. The ring frame is connected to the second end portion of each of the plurality of fan blades. The ring frame includes a first surface facing the plurality of fan blades and a second surface opposite to the first surface, and the first surface is a curved surface.