Patents by Inventor Chen Lin

Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379836
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei Wang, Wei-Chen Yang, Yao-Chung Chang, Ru-Yi Su, Yen-Ku Lin, Chuan-Wei Tsou, Chun Lin Tsai
  • Publication number: 20240379762
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Publication number: 20240381632
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han LIN, Te-An CHEN
  • Publication number: 20240379450
    Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan
  • Publication number: 20240381561
    Abstract: An expansion card frame assembly is configured to support a riser card and an expansion card. The expansion card frame assembly includes a frame, a pivotable component and a stopper. The frame is configured to support the riser card, and the expansion card is configured to be inserted into the riser card. The pivotable component is pivotably disposed on the frame and configured to be located aside the expansion card. The stopper is movably disposed on the pivotable component and configured to be located at one side of the expansion card which is located farther away from the riser card.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 14, 2024
    Inventors: CHENG-YAO TSAI, Wei Chen Lin, PING SHENG YEH, YEN-HSIANG WANG, YI-SHEN CHEN
  • Publication number: 20240379641
    Abstract: The disclosure provides an electronic device, including a substrate, a first conductor layer, a first insulating layer, an electronic component, and a driving structure. The first conductor layer is arranged on the substrate. The first insulating layer is disposed on the first conductor layer. The electronic component is arranged on the first insulating layer and coupled to the first conductor layer. The driving structure is coupled to the electronic component. The electronic device in the disclosure can have improved structural reliability.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Applicant: Innolux Corporation
    Inventors: Jen-Hai Chi, Chen-Lin Yeh, Chih-Yung Hsieh
  • Publication number: 20240381349
    Abstract: A method performed by a User Equipment (UE) for a Simultaneous Transmission with Multi-Panel (STxMP) operation is provided. The method receives a configuration for multi-DCI based STxMP Physical Uplink Shared Channel (PUSCH). The method receives a Sounding Reference Signal (SRS) resource set configuration including a first SRS resource set and a second SRS resource set. The method receives first DCI in a first Control Resource Set (CORESET) and second DCI in a second CORESET. The method determines a size of a first field in the first DCI and a size of a second field in the second DCI based on the number of first SRS resources in the first SRS resource set and the number of second SRS resources in the second SRS resource set, respectively. The method transmits a first PUSCH and a second PUSCH scheduled by the first DCI and the second DCI, respectively.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 14, 2024
    Inventors: YEN-HUA LI, MEI-JU SHIH, WAN-CHEN LIN, CHIA-HUNG LIN, PO-CHUN CHOLI
  • Publication number: 20240379569
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An electrical insulating and thermal conductive layer is formed over a semiconductor substrate. A dielectric structure is formed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. An opening is formed in the dielectric structure, wherein the opening extending through the dielectric structure and the electrical insulating and thermal conductive layer. A circuit layer is formed in the dielectric structure, wherein the circuit layer fills the opening.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Publication number: 20240377662
    Abstract: An optical device and methods of manufacturing such optical devices are presented. In embodiments the optical device is a tunable beam splitter which is made by forming a first dopant region over a substrate, the first dopant region comprising a first waveguide and a second waveguide, depositing a cladding material over the first waveguide and the second waveguide, and forming a second dopant region overlying the first waveguide and the second waveguide, wherein the forming the second dopant region comprises forming a first region extending over both the first waveguide and the second waveguide, the first region having a constant concentration of a first dopant.
    Type: Application
    Filed: January 17, 2024
    Publication date: November 14, 2024
    Inventors: Ming Lee, Tien-Lin Shen, Wei-Heng Lin, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20240379376
    Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Rajesh Prasad, Yung-Chen Lin, Zhiyu Huang, Fenglin Wang, Chi-I Lang, Hoyung David Hwang, Edwin A. Arevalo, KyuHa Shim
  • Publication number: 20240379494
    Abstract: A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Yu Chen Lee, Shu-Shen Yeh, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240377660
    Abstract: An optical device and method of manufacture is presented. In embodiments a method includes forming a first layer of optical material, patterning the first layer into a stair-step pattern, depositing a dielectric material onto the stair-step pattern, and forming a second layer of optical material over the dielectric material and at least partially within the stair-step pattern.
    Type: Application
    Filed: January 2, 2024
    Publication date: November 14, 2024
    Inventors: Ming Lee, Tien-Lin Shen, Wei-Heng Lin, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20240379475
    Abstract: A package structure is provided. The package structure includes a substrate and a ground structure laterally surrounded by the substrate. The package structure also includes a chip-containing structure over the substrate and a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The ground structure is electrically connected to the protective lid through the first adhesive element. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chen-Shien CHEN
  • Publication number: 20240381656
    Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Han-Jong Chia, Chung-Te Lin, Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang
  • Publication number: 20240377946
    Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chen-Hao Chen, Shih-Hsiang Shen, Hui-Lin Liu
  • Publication number: 20240378162
    Abstract: A bridge device for bridging a host device and a data storage device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface. The second transmission interface is coupled to the first transmission interface through a bus. The first transmission interface operates in a slave mode and the second transmission interface operates in a master mode. The first transmission interface and the second transmission interface generate multiple transfer data chunks in compliance with a common bridge transfer format to perform transfer operations in dual directions for respectively transferring a command and data between a host device and a data storage device.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 14, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chen-Hao Chen, Shih-Hsiang Shen, Hui-Lin Liu
  • Patent number: 12142845
    Abstract: The present disclosure relates to a compact antenna system within a dielectric housing of an electronic device, capable of achieving improved reflection performance. The antenna system includes a ground plane and an antenna PCB. An antenna microstrip feed on a side of the antenna PCB comprises a first part of a radiating antenna element. The antenna PCB is connected to the ground plane by a central conductor of a coaxial cable which forms a ground path. An outer conductor of the coaxial cable carries RF signals to the antenna PCB, allowing the RF signals to freely radiate along a length of the coaxial cable and acting as a second part of the radiating antenna element. The coaxial cable does not interfere with, and can even enhance a radiation pattern of the antenna microstrip feed.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 12, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yung-Chang Wei, Chin-Hung Ma, I-Chen Lin, Po Chao Chen
  • Patent number: 12141578
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 12137914
    Abstract: An anastomosis set for anastomosing a first end to be anastomosed with a second end to be anastomosed, such anastomosis set comprising: a first manipulator, with a first telescoping part at a distal end thereof, the first telescoping part is used for telescoping toward the first end to be anastomosed; a second manipulator, with a second telescoping part at a distal end thereof, the second telescoping part is used for telescoping toward the second end to be anastomosed; and an anastomosis mechanism for anastomosing the first end to be anastomosed with the second end to be anastomosed; the first manipulator including a first exit part through which the first manipulator will be removed from the first end to be anastomosed after anastomosing; the second manipulator has a second exit part, through which the second manipulator will be removed from the second end to be anastomosed after anastomosing.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 12, 2024
    Assignee: Vasocollar, Inc
    Inventors: Hsin-Lei Huang, Wei-Chen Hong, Cheng Tung Huang, Hang-Yi Lin, Hsin-Hui Huang
  • Patent number: D1051255
    Type: Grant
    Filed: June 24, 2024
    Date of Patent: November 12, 2024
    Assignee: Shenzhen Yile Dynamic Technology Co., LTD
    Inventors: Jianfeng Lin, Jinsong Fan, Chen Huang