Patents by Inventor Chen Lin

Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optical Device and Method of Manufacture
    Publication number: 20240107781
    Abstract: Optical devices and methods of manufacture are presented in which an opening is formed within a first semiconductor device and then bonded to other optical devices. A laser die or other fill material may be used to refill the opening. The first semiconductor device is then electrically connected to an optical interposer.
    Type: Application
    Filed: March 28, 2023
    Publication date: March 28, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Jui Lin Chao
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20240107890
    Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.
    Type: Application
    Filed: October 24, 2022
    Publication date: March 28, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Ching-Hua Hsu, Jing-Yin Jhang
  • FAN MODULE
    Publication number: 20240102483
    Abstract: A fan module includes a hub, a plurality of fan blades, and a ring frame. The hub is configured to rotate about a central axis. The plurality of fan blades surround the hub. Each of the plurality of fan blades includes a first end portion connected to the hub and a second end portion opposite to the first end portion. The ring frame is connected to the second end portion of each of the plurality of fan blades. The ring frame includes a first surface facing the plurality of fan blades and a second surface opposite to the first surface, and the first surface is a curved surface.
    Type: Application
    Filed: April 9, 2023
    Publication date: March 28, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Hsin-Chen Lin, Ing-Jer Chiou
  • Method for improving usability and accuracy for physiological measurement
    Patent number: 11940388
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2024
    Assignee: IXENSOR CO., LTD.
    Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
  • Semiconductor device and method of manufacturing the same
    Patent number: 11943936
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Der Chih, May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen Zhang Lin, Chrong Jung Lin, Ya-Chin King, Chieh Lee, Wang-Yi Lee
  • Generation of microservices from a monolithic application based on runtime traces
    Patent number: 11940904
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate generation of microservices from a monolithic application based on runtime traces are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a model component that learns cluster assignments of classes in a monolithic application based on runtime traces of executed test cases. The computer executable components can further comprise a cluster component that employs the model component to generate clusters of the classes based on the cluster assignments to identify one or more microservices of the monolithic application.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 26, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Xiao, Anup Kalia, Chen Lin, Raghav Batta, Saurabh Sinha, John Rofrano, Maja Vukovic
  • Antenna device
    Patent number: 11942699
    Abstract: An antenna device includes a first insulation layer, a defected metal layer, a second insulation layer, and a plurality of radiators. The defected metal layer is disposed on the first insulation layer, and the defected metal layer has a plurality of recess features which are arranged with uniform pitches. The second insulation layer is disposed on the first insulation layer and the defected metal layer. The radiators are disposed on the second insulation layer, and each radiator has a feeding portion and a grounding portion.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 26, 2024
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Hsin-Hung Lin, Wei Chen Cheng
  • Previewing method and apparatus for effect application, and device, and storage medium
    Patent number: 11941728
    Abstract: The present disclosure provides an effect application previewing method, an apparatus, a device and a storage medium. The method includes: taking, in response to a preview trigger operation for a target effect style, a position of a pointer on a video track as a start point, to generate a virtual video frame for the target effect style; synchronously playing the virtual video frame and at least one video clip corresponding to the virtual video frame on the video track based on a timeline, to preview an effect of the target effect style applied to the at least one video clip.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: March 26, 2024
    Assignee: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.
    Inventors: Zhaoqin Lin, Pingfei Fu, Yan Zeng, Qifan Zheng, Chen Zhao
  • Fin isolation structure for FinFET and method of forming the same
    Patent number: 11942373
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Method and apparatus for PDCCH monitoring
    Patent number: 11943785
    Abstract: A method for PDCCH monitoring performed by a UE is provided. The method includes performing the PDCCH monitoring in a first group associated with at least one first PDCCH monitoring configuration; receiving, from a base station, DCI comprising an indicator; performing the PDCCH monitoring in a second group associated with at least one second PDCCH monitoring configuration; and stopping the PDCCH monitoring in the first group after receiving the indicator.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 26, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Wan-Chen Lin, Chie-Ming Chou, Tsung-Hua Tsai, Yu-Hsin Cheng
  • ANTENNA SYSTEM
    Publication number: 20240097351
    Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 21, 2024
    Inventors: Hsin Hung LIN, Yu Shu TAI, Wei Chen CHENG
  • SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240096806
    Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: CHAO-HSUAN CHEN, WEI CHEN HUNG, LI-WEI YIN, YU-HSIEN LIN, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • MANUFACTURING METHOD OF ELECTRONIC ELEMENT MODULE
    Publication number: 20240097067
    Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
  • BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
    Publication number: 20240097661
    Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20240099154
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Adding Sealing Material to Wafer edge for Wafer Bonding
    Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
    Publication number: 20240096689
    Abstract: The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: TE-AN CHEN, MENG-HAN LIN
  • Packages With Photonic Engines and Method of Forming the Same
    Publication number: 20240094469
    Abstract: A method includes patterning a top silicon layer in a substrate to form a plurality of photonic devices. The substrate includes the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer. The method further includes forming a second dielectric layer to embed the plurality of photonic devices therein, forming an interconnect structure over and signally coupling to the plurality of photonic devices, bonding an electronic die to the interconnect structure, thinning the semiconductor layer, and patterning the semiconductor layer that has been thinned to form openings. The openings are filled with a dielectric material to form dielectric regions. Through-vias are formed to penetrate through the dielectric regions to electrically couple to the interconnect structure.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Jui Lin Chao
  • Driving mechanism for optical element
    Patent number: 11934034
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, a driving assembly, and an assist assembly. The movable portion is used for connecting to an optical element having a main axis. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The assist assembly limits the movement of the movable portion relative to the fixed portion.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chen-Hsien Fan, Yueh-Lin Lee, Yu-Chiao Lo, Sung-Mao Tsai, Shang-Hung Chen
  • Single instruction multiple data SIMD instruction generation and processing method and related device
    Patent number: 11934837
    Abstract: An SIMD instruction generation and processing method and a related device are provided. The method may include: obtaining a length of each loop dimension of a first tensor formula; selecting, from a plurality of groups of information about a first SIMD instruction model based on the length of each loop dimension of a first tensor formula, information about a second SIMD instruction model matching the first tensor formula; generating, based on a length of at least one loop dimension of the first tensor formula and the second SIMD instruction model, a first SIMD instruction obtained after the first tensor formula is converted. The information about a second SIMD instruction model is selected from the plurality of groups of information about a first SIMD instruction model based on the length of each loop dimension of the tensor formula.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: March 19, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chen Wu, Yifan Lin, Xiaoqiang Dan