Abstract: An embedded touch panel display device includes: a display unit having a display surface and a non-display surface opposite to the display surface; a touch-control unit disposed inside the display unit; a conductive frame disposed on one side of the display unit and facing the non-display surface thereof, an insulating ink and a first conductive ink disposed on at least one sidewall of the display unit and extended to the non-display surface, in which the first conductive ink overlaps the insulating ink; and a double-sided adhesive disposed between the display unit and the conductive frame to secure them. The first conductive ink and the conductive frame are electrically connected to each other to form an electrostatic discharge path. The present invention can prevent the peripheral area of the viewed area from a blackening phenomenon induced by excessively high electrostatic voltage.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

Abstract: A control system may include a direct-current (DC) power bus for charging internal energy storage elements in control devices of the control system. For example, the control devices may be motorized window treatments configured to adjust a position of a covering material to control the amount of daylight entering a space. The system may include a bus power supply that may generate a DC voltage on the DC power bus. For example, the DC power bus may extend from the bus power supply around the perimeter of a floor of the building and may be connected to all of the motorized window treatments on the floor (e.g., in a daisy-chain configuration). An over-power protection circuit may be configured to disconnect the bus power supply if a bus current exceeds a threshold for a period of time.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

Abstract: An electronic lock includes a lock assembly configured to switch between a locking state and an unlocking state, and a control unit electrically connected to the lock assembly. The control unit includes an operation panel configured to receive a user input, a light sensor configured to measure intensity of ambient light and generate a light-sense signal, a proximity sensor configured to generate a wake signal, a backlight module configured to emit light from the operation panel, and a control module electrically connected to the lock assembly, the operation panel, the light sensor, the proximity sensor, and the backlight module. The control module is configured to control operation of the lock assembly based on the user input, activate the light sensor to measure the intensity of the ambient light, activate the backlight module to emit the light, and control the backlight module to adjust brightness of the light emitted thereby.

Abstract: The disclosure provides a method for adjusting pixel values of blending image. The method includes projecting, on a projection surface, a first projection image onto a first projection range and a second projection image onto a second projection range by a first projector and a second projector, and blending the first projection image and the second projection image to generate a blending image; calculating positions of a plurality of boundaries of the first projection range and the second projection range; adjusting a range of an overlapping area between the first projection range and the second projection range; and adjusting image parameters of a non-overlapping area outside the overlapping area, to enable pixel values of the non-overlapping area to be close to pixel values of the overlapping area.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

Abstract: A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure formed over the fin structure and adjacent to the gate structure, and an S/D contact structure formed over the S/D structure and adjacent to the gate structure. The FinFET device structure also includes a protection layer formed on the S/D contact structure, and the protection layer and the S/D contact structure are made of different materials. The protection layer has a bottommost surface in direct contact with a topmost surface of the S/D contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the semiconductor structure includes forming a fin structure extending from a front side of a substrate, recessing a source region of the fin structure to form a source opening, forming a semiconductor plug under the source opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact. By performing the PAI process, crystalline semiconductor is amorphized and may be substantially removed. Thus, the performance and reliability of the semiconductor structure may be advantageously improved.

Abstract: The current disclosure describes carrier tape systems, which include a carrier tape including a plurality of pockets. Each pocket contains a semiconductor device adhered to a bottom surface of the pocket by an adhesive. In some embodiments, the adhesive is a reversible adhesive. Use of the adhesive reduces the likelihood the semiconductor device will be damaged due to movement of the semiconductor device in the pocket during shipment of the carrier tape. Methods of forming a semiconductor device carrier systems and methods of supplying semiconductor devices are also described.

Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.

Abstract: An electronic lock includes a deadbolt, a driver mechanism, a transmission mechanism and a control mechanism. The transmission mechanism includes a transmission gear that is driven by the driver mechanism to rotate, a resilient unit that is mounted to and co-rotatable with the transmission gear, and a rotary member that is operable to rotate relative to the transmission gear between a locking position and an unlocking position, and that is connected to the deadbolt. The control mechanism is connected to the rotary member, and ceases operation of the driver mechanism when detecting that the rotary member has been rotated to one of the locking and unlocking positions.

Abstract: A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

Abstract: An electronic lock device includes a lock mechanism, an actuation mechanism that actuates the lock mechanism, and a control unit including a processor and a current detection module. During an operation in which the actuation mechanism is activated to start switching the lock mechanism from an original state to an intended state, the current detection module continuously detects an amount of electric current flowing through the actuation mechanism. When the amount of electric current is greater than a predetermined threshold, the processor controls the actuation mechanism to switch the lock mechanism back to the original state, and deactivates the actuation mechanism.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Abstract: A method of generating a layout pattern includes disposing a photoresist layer of a resist material on a substrate and disposing a top layer over of the photoresist layer. The top layer is transparent for extreme ultraviolet (EUV) radiation and the top layer is opaque for deep ultraviolet (DUV) radiation. The method further includes irradiating the photoresist layer with radiation generated from an EUV radiation source. The radiation passes through the top layer to expose the photoresist layer.