Patents by Inventor Chen Wei

Chen Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240091315
    Abstract: The present invention relates to extended recombinant polypeptide (XTEN) compositions, conjugate compositions comprising XTEN and XTEN linked to cross-linkers useful for conjugation to pharmacologically active payloads, methods of making highly purified XTEN, methods of making XTEN-linker and XTEN-payload conjugates, and methods of using the XTEN-cross-linker and XTEN-payload compositions.
    Type: Application
    Filed: March 13, 2023
    Publication date: March 21, 2024
    Inventors: Volker Schellenberger, Vladimir Podust, Chia-Wei Wang, Bryant McLaughlin, Bee-Cheng Sim, Sheng Ding, Chen Gu
  • Publication number: 20240099154
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Patent number: 11937515
    Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11936418
    Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 19, 2024
    Assignee: KAIKUTEK INC.
    Inventors: Mike Chun-Hung Wang, Chun-Hsuan Kuo, Mohammad Athar Khalil, Wen-Sheng Cheng, Chen-Lun Lin, Chin-Wei Kuo, Ming Wei Kung, Khoi Duc Le
  • Publication number: 20240085621
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulant, and forming an interconnect structure over and electrically connecting to the first device die and the second device die. A waveguide is formed in the interconnect structure. An optical-engine based interconnect component is bonded to the interconnect structure. The optical-engine based interconnect component forms a part of a signal path that connects the first device die to the second device die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 14, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Chih-Wei Tseng, Jui Lin Chao
  • Publication number: 20240090019
    Abstract: A method for LBT failure detection performed by a UE is provided. The method includes: receiving, by a MAC entity of the UE, an LBT failure indication from a lower layer for all UL transmissions; increasing an LBT failure counter when the MAC entity receives the LBT failure indication; determining an LBT failure event occurs when the LBT failure counter is greater than or equal to a threshold; and resetting the LBT failure counter after the MAC entity has not received the LBT failure indication for a time period.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Chen Chen, Chie-Ming Chou, Chia-Hung Wei, Mei-Ju Shih
  • Publication number: 20240087934
    Abstract: A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: YONG-JYU LIN, FU-HSIEN LI, CHEN-WEI LU, CHI-FENG TUNG, HSIANG YIN SHEN
  • Publication number: 20240087904
    Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 14, 2024
    Inventors: Seongjun Heo, Jengyi Yu, Chen-Wei Liang, Alan J. Jensen, Samantha S.H. Tan
  • Publication number: 20240088104
    Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 11928752
    Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: March 12, 2024
    Assignee: GRABTAXI HOLDINGS PTE. LTD.
    Inventors: Kong-Wei Lye, Yang Cao, Swara Desai, Chen Liang, Xiaojia Mu, Yuliang Shen, Sien Y. Tan, Muchen Tang, Renrong Weng, Chang Zhao
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11929261
    Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 11929016
    Abstract: A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: March 12, 2024
    Assignee: MACROBLOCK, INC.
    Inventors: Chi-Min Hsieh, Che-Wei Chang, Chen-Yuan Kuo, Wei-Hsiang Cheng
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240077670
    Abstract: A semiconductor structure includes an optical interposer having at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed above the first dielectric layer. The semiconductor structure further includes a first die disposed on the optical interposer and electrically connected to the optical interposer; a first substrate under the optical interposer; and conductive connectors under the first substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: March 7, 2024
    Inventors: Chih-Wei Tseng, Hsing-Kuo Hsia, Stefan Rusu, Chen-Hua Yu, Chewn-Pu Jou
  • Publication number: 20240077669
    Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 7, 2024
    Inventors: Chen-Hua Yu, Jiun Yi Wu, Szu-Wei Lu
  • Publication number: 20240075082
    Abstract: Provided is a composition including a lactic acid bacterium and a carrier thereof for prophylaxis or treatment of an allergy. The lactic acid bacterium is Lactobacillus paragasseri, such as Lactobacillus paragasseri BBM171 deposited under DSMZ Accession No. DSM 34311. Also provided is a method for preventing or treating an allergy in a subject that includes administering an effective amount of the composition of Lactobacillus paragasseri to the subject.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 7, 2024
    Inventors: Ying-Chieh Tsai, Yu-Hsuan Wei, Chih-Chieh Hsu, Chien-Chen Wu
  • Patent number: 11923794
    Abstract: A motor control apparatus receives a DC power source through a DC terminal and is coupled to a motor. The motor control apparatus includes a brake, an inverter, and a controller. The brake is coupled to the inverter. The brake includes an energy-consuming component and a switch component. The controller controls the inverter to convert the DC power source to drive the motor. When the controller determines that the DC power source is interrupted, the controller stops controlling the inverter, and the switch component is self-driven turned on so that a back electromotive force generated by the motor is consumed through the energy-consuming component.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Te-Wei Wang, Yi-Kai Peng, Chen-Yeh Lee
  • Patent number: D1019739
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 26, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chen-Hsien Cheng, Li-Fang Chen, Ruei-Hong Hong, Ting-Wei Wu