Abstract: A semiconductor device can include a passive device, having a top device including a top doped region, a top gate region, and a frontside contact, a bottom device including a bottom doped region, a bottom gate region, and a backside contact.

Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to track a sequence of steps of charging an electric vehicle (EV) by electric vehicle service equipment (EVSE), execute a large-language model (LLM) to generate handling operations for a user to handle components of the EVSE, and output the handling operations to an extended-reality (XR) device. The handling operations support the steps of charging the EV. The XR device displays the handling operations overlaid on the EVSE. The XR device highlights the components of the EVSE that are in the handling operations.

Abstract: Embodiments of the invention disclose structures and methods for making the structures. According to an embodiment, the structure may include a top transistor stacked on a bottom transistor, wherein top nanosheet stacks of the top transistor are vertically aligned to bottom nanosheet stacks of the bottom transistor, and wherein a top source/drain region of the top transistor is connected to backside interconnects by an extension region, a backside contact, and a backside via.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A p-channel field-effect transistor (pFET) having a source/drain region is formed, where: a bottom surface of the source/drain region is of a depth lower than a bottom surface of a gate region; and the source/drain region comprises a silicon germanium alloy doped with boron; An n-channel field-effect transistor (nFET) is formed. A via is formed, where the via has a top surface above a top surface of the nFET. The semiconductor structure is flipped. A substrate is selectively removed respective to the source/drain region. A backside interlayer dielectric (ILD) is formed, where the backside ILD is of a different material than a shallow trench isolation layer. A backside contact is formed, where the backside contact contacts the source/drain region and the via.

Abstract: A semiconductor device includes a lower device layer having a bottom transistor and an upper device layer having a transistor, positioned above and laterally offset from the bottom transistor. A backside power plane is below the lower device layer. A backside bottom gate contact penetrates through the backside power plane to contact a gate of the bottom transistor. A dielectric liner is between the backside power plane and the backside bottom gate contact.

Abstract: A semiconductor device can include a passive device, having a passive device having a top device including a first top doped region and a second top doped region separated by a top gate region, and a first frontside contact and a second frontside contact over the first top doped region and the second top doped region, respectively, and a bottom device including a first bottom doped region and second bottom doped region separated by a bottom gate region, and a first backside contact and a second backside contact below the first bottom doped region and the second bottom doped region, respectively, a first well region and a second well region electrically connecting the top device to the bottom device.

Abstract: The present disclosure provides a display device and an injection mold. The display device includes: a display substrate; a cover plate, provided on a side of the display substrate, a chamfer being provided at a corner position of the cover plate, the chamfer being on a side of the cover plate close to the display substrate, the chamfer having a height in a thickness direction of the cover plate, a ratio of the height of the chamfer to a maximum thickness of the cover plate being greater than or equal to 0.03 and less than or equal to 0.5, the chamfer having a bevel edge, and an included angle between the bevel edge and a plane where the display device is located being greater than or equal to 50 degrees and less than or equal to 80 degrees; and an injection molded edge sealing member second.

Abstract: Disclosed are a tricyclic fused heterocyclic compound having a PDE3/4 dual inhibitory effect represented by formula (I), a stereoisomer, a solvate, or a pharmaceutically acceptable salt thereof, and the use thereof in the preparation of a drug for treating/preventing PDE3/4-mediated diseases. Each group in formula (I) is as defined in the description.

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

Abstract: A semiconductor structure includes a transistor device having a first nanosheet device disposed on a second nanosheet device in a stacked configuration. The first nanosheet device includes a plurality of first nanosheet channel layers, wherein each of the plurality of first nanosheet channel layers have a nanosheet channel portion on one end and a dielectric material portion on another end. The second nanosheet device includes a plurality of second nanosheet channel layers. The dielectric material portion of the plurality of first nanosheet channel layers is part of a non-active region.

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Abstract: The present invention discloses aggregation-induced emission fluorescent compounds with near-infrared (NIR) emission. This fluorescent compound is then encapsulated by polymer matrix to yield nanoaggregates which is confirmed to show an excellent photothermal conversion efficiency while maintaining a high fluorescence quantum yield. Consequently, the photothermal therapeutic efficacy can be improved by PTA-oriented accumulation of nanoaggregates, compared with the barely enhanced permeability and retention (EPR) effect. The in vitro and in vivo verification further confirmed that the nanoaggregates exhibit superior fluorescence-guided phototheranostics ability to eliminate tumors.

Abstract: A stacked FET architecture includes isolated pockets for replacement metal gates for top and bottom nanosheet field-effect transistors. Different work function metals are employed for the metal gates of n-type and p-type FETs. The architecture allows flexibility in providing electrically connected or unconnected metal gates.

Abstract: A backing film removal system comprises a separating mechanism configured to separate a first portion of a first backing film on a first side of a material segment and a second portion of a second backing film on a second side of the material segment from a material layer of the material segment, wherein the second side is opposite the first side. The backing film removal system also includes a clamping mechanism that is actuatable to apply a clamping force to secure the material layer and the second portion together. A separator assembly includes a gripping mechanism configured to grip the first portion. At least one of the gripping mechanism or the clamping mechanism is movable to draw the first portion gripped by the gripping mechanism away from the material layer to remove a remaining portion of the first backing film from the material layer.

Abstract: Embodiments of the present application provide an electronic device for wireless communication. An example electronic device includes a low-frequency processing circuit, a high-frequency processing circuit, a coil, and at least one capacitor. The low-frequency processing circuit is electrically connected to two ends of the coil. The high-frequency processing circuit is electrically connected to the two ends of the coil. Each of the at least one capacitor is connected in parallel to the coil.

Abstract: A data encoding method includes obtaining to-be-encoded data; processing the to-be-encoded data by using a volume preserving flow model to obtain a hidden variable output, where the volume preserving flow model includes a target volume preserving flow layer, an operation corresponding to the target volume preserving flow layer is an invertible operation that meets a volume preserving flow constraint, the target volume preserving flow layer is used to perform a multiplication operation on a preset coefficient and first data input to the target volume preserving flow layer, and the preset coefficient is not 1; and encoding the hidden variable output to obtain encoded data.

Abstract: A semiconductor device includes a top transistor stacked over a bottom transistor. The top transistor comprises horizontally oriented nanosheet gates, and the bottom transistor comprises vertically oriented nanosheet gates. The top transistor and the bottom transistor are staggered.

Abstract: A stacked field effect transistor structure includes a lower field effect transistor including a lower first drain-source region, a lower second drain-source region, at least one lower channel region interconnecting the lower first and lower second drain-source regions, and a lower gate structure adjacent the at least one lower channel region. An upper field effect transistor includes an upper first drain-source region, an upper second drain-source region, and at least one upper channel region interconnecting the upper first and upper second drain-source regions, and an upper gate structure adjacent the at least one upper channel region. A gate interconnect connects the lower gate structure to the upper gate structure. The gate interconnect includes: a gate contact directly connected to the lower gate structure; and a contact plug directly connected to the top gate structure and electrically coupled to the gate contact.

Abstract: A method for die-to-die (D2D) image alignment using a defect map associated with an image. The method includes accessing a set of images of a substrate, which correspond to different image capture conditions. The locations of various defects on the set of images are obtained and a defect map indicating relative locations of at least some of the defects is generated. The set of images are aligned with each other using the defect map to generate an aligned set of images.

Abstract: A method for training a prediction model to generate a high-resolution image representing defects on a substrate from a low-resolution image of the substrate. The method includes inputting a first image and a reference image of defects on a substrate, which are representative of images captured using different image capture conditions, to a neural network. The neural network is executed to generate a predicted image in response to the first image. A loss function that is indicative of a difference between a defect distribution in the predicted image and a defect distribution in the reference image is calculated and the neural network is modified based on the loss function. The neural network may be trained until the loss function is minimized.