Patents by Inventor Chen Zhang

Chen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199407
    Abstract: A frequency stabilization method and system for tunable light sources based on characteristic curve reconstruction are provided, which relate the field of frequency stabilization technologies of modulation absorption spectrum. A set of frequency stabilization control method and system based on internal modulation absorption spectroscopy of light source is constructed, and a high-precision laser frequency stabilization method under large-amplitude and high-bandwidth frequency modulation based on frequency discrimination curve reconstruction is proposed to solve a problem that it is difficult for micro-probe laser interferometry measurement benchmark to balance large-amplitude and high-bandwidth frequency modulation, and high-precision frequency stabilization, resulting in that it is difficult to obtain high relative accuracy measurement under large-range measurement.
    Type: Grant
    Filed: June 24, 2024
    Date of Patent: January 14, 2025
    Assignee: Harbin Institute of Technology
    Inventors: Yisi Dong, Wenwen Li, Wenrui Luo, Chen Zhang, Jinran Zhang, Pengcheng Hu, Ruitao Yang
  • Publication number: 20250000988
    Abstract: Disclosed are a bicyclic peptide ligand having high affinity for Eph receptor tyrosine kinase A2 (EphA2), a drug conjugate containing the bicyclic peptide ligand and a pharmaceutically acceptable salt thereof, and a pharmaceutical composition containing same, and the use of the drug conjugate and the pharmaceutical composition in the preparation of a drug for preventing and/or treating EphA2 overexpressed disease.
    Type: Application
    Filed: October 14, 2022
    Publication date: January 2, 2025
    Applicant: Xizang Haisco Pharmaceutical Co., Ltd.
    Inventors: Yao LI, Lei CHEN, Haitao HUANG, Haodong WANG, Pingming TANG, Yan YU, Chen ZHANG, Pangke YAN
  • Publication number: 20250006736
    Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Inventors: Biswanath Senapati, Shahrukh Khan, Utkarsh Bajpai, Terence Hook, Chen Zhang, Junli Wang
  • Patent number: 12183004
    Abstract: Provided in the present application are a method and a device for extracting a blood vessel wall, a medical imaging system, and a non-transitory computer-readable storage medium. The method for extracting a blood vessel wall comprises acquiring a medical image, determining at least one first-order feature in the medical image, and extracting, on the basis of the at least one first-order feature, a blood vessel wall image from the medical image.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 31, 2024
    Assignee: GE Precision Healthcare LLC
    Inventors: Zhoushe Zhao, Yingbin Nie, Chen Zhang
  • Patent number: 12182983
    Abstract: A method for evaluating images of a printed pattern. The method includes obtaining a first averaged image of the printed pattern, where the first averaged image is generated by averaging raw images of the printed pattern. The method also includes identifying one or more features of the first averaged image. The method further includes evaluating the first averaged image, using an image quality classification model and based at least on the one or more features. The evaluating includes determining, by the image quality classification model, whether the first averaged image satisfies a metric.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 31, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Chen Zhang, Qiang Zhang, Jen-Shiang Wang, Jiao Liang
  • Publication number: 20240429277
    Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Ruqiang Bao, Jingyun Zhang, Junli Wang, Chen Zhang, Uzma Rana
  • Publication number: 20240431087
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Huimei Zhou, Carl Radens, Chen Zhang, Junli Wang, Miaomiao Wang
  • Publication number: 20240429226
    Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a protection diode. The protection diode includes a substrate, a gate, a first nanosheet layer, and a second nanosheet layer. The first nanosheet layer includes a heavily doped n-type epitaxial disposed over the substrate. Additionally, the first nanosheet layer is in contact with the gate. Further, the second nanosheet layer includes a heavily doped p-type epitaxial disposed over the substrate. Additionally, the second nanosheet layer is in contact with the gate. Further, the first nanosheet layer and the second nanosheet layer surround the gate.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Inventors: HUIMEI ZHOU, Chen Zhang, Shahrukh Khan, Albert M. Chu, Anthony I. Chou, Junli Wang
  • Publication number: 20240426895
    Abstract: A semiconductor test structure includes a first transistor active area comprising at least a first source/drain region, and a second transistor active area stacked on the first transistor active area and comprising at least a second source/drain region. At least one dielectric layer is disposed between the first transistor active area and the second transistor active area. The semiconductor test structure further includes a plurality of contact structures spaced apart from each other and disposed on the second source/drain region, and at least one gate structure extending across the first transistor active area and the second transistor active area. Contact resistance is measured between respective ones of the plurality of contact structures and the second source/drain region, and the second source/drain region is continuous between the plurality of contact structures.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Inventors: Huimei Zhou, Chen Zhang, Miaomiao Wang, Junli Wang
  • Patent number: 12176416
    Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: December 24, 2024
    Assignee: International Business Machines Corporation
    Inventors: Lan Yu, Kangguo Cheng, Heng Wu, Chen Zhang
  • Publication number: 20240421025
    Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.
    Type: Application
    Filed: December 16, 2021
    Publication date: December 19, 2024
    Inventors: Lianchang DU, Jeffory L. SMALLEY, Srikant NEKKANTY, Eric W. BUDDRIUS, Yi ZENG, Xinjun ZHANG, Maoxin YIN, Zhichao ZHANG, Chen ZHANG, Yuehong FAN, Mingli ZHOU, Guoliang YING, Yinglei REN, Chong J. ZHAO, Jun LU, Kai WANG, Timothy Glen HANNA, Vijaya K. BODDU, Mark A. SCHMISSEUR, Lijuan FENG
  • Publication number: 20240416787
    Abstract: Systems and methods for optimizing transportation efficiency, for example, in the context of energy shortages. Techniques described herein may involve determining a high-price threshold is exceeded, identifying different vehicle types (e.g., high-efficiency vehicles, large battery capacity vehicles, etc.), prioritizing vehicles designated for charging and discharging, respectively, setting vehicle calibrations accordingly, and tracking/reporting performance relative to baselines.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 19, 2024
    Applicant: Ford Global Technologies, LLC
    Inventors: Dominique Meroux, Kai Wu, Chen Zhang
  • Publication number: 20240410700
    Abstract: Provided is a system including a robot and an application of a communication device. The robot includes a medium storing instructions that when executed by a processor of the robot effectuate operations including: obtaining first data indicative of a relative position of the robot in a workspace; actuating the robot to drive within the workspace to form a map including mapped perimeters that correspond with physical perimeters of the workspace while obtaining second data indicative of movement of the robot; and forming the map of the workspace based on at least some of the first data, wherein the map of the workspace expands as new first data are obtained, until all perimeters of the workspace are included in the map. The application is configured to display information, such as the map, and receive user input.
    Type: Application
    Filed: August 23, 2024
    Publication date: December 12, 2024
    Applicant: AI Incorporated
    Inventors: Ali Ebrahimi Afrouzi, Lukas Robinson, Chen Zhang, Sebastian Schweigert
  • Publication number: 20240408085
    Abstract: A compound of general formula (I) or a stereoisomer, a deuterated compound, a solvate, a prodrug, a metabolite, a pharmaceutically acceptable salt, or a co-crystal thereof, an intermediate thereof, and a use thereof in Bcl-2 family proteins-related diseases such as cancer.
    Type: Application
    Filed: September 1, 2022
    Publication date: December 12, 2024
    Inventors: Chen ZHANG, Yuting LIAO, Yonghua LU, Junbin ZHAO, Sijia ZOU, Yan YU, Pingming TANG, Qiu GAO, Xinfan CHENG, Fei YE, Yao LI, Jia NI, Pangke YAN
  • Patent number: 12166658
    Abstract: A binding segment identifier processing method and a device are provided. The method includes a network device receives a message sent by a controller, where the message includes type information and a segment identifier, and the type information indicates that the segment identifier is a binding segment identifier BSID. The network device performs a processing action on the BSID based on the type information. According to embodiments of this application, the network device can identify the BSID, to resolve a technical problem that an incorrect processing result is caused when a segment identifier list of the network device includes the BSID.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: December 10, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ka Zhang, Chen Zhang, Zhibo Hu, Sheng Fang, Zuliang Wang
  • Publication number: 20240400586
    Abstract: Provided are a compound represented by formula (I), a stereoisomer, pharmaceutically acceptable salt, solvate and eutectic or deuterated material thereof, or a pharmaceutical composition comprising same, and a use thereof as a PARP-1 inhibitor in the preparation of a drug for treating related diseases.
    Type: Application
    Filed: September 29, 2022
    Publication date: December 5, 2024
    Inventors: Yao LI, Wenjing WANG, Lei CHEN, Peng KANG, Chao FU, Tiancheng HE, Linyong FANG, Naicheng GUI, Pingming TANG, Yan YU, Chen ZHANG, Pangke YAN
  • Publication number: 20240405071
    Abstract: A semiconductor structure includes a nanosheet field-effect transistor having a nanosheet stack structure, and a fin field-effect transistor having a set of vertical fins. Each of the vertical fins includes an oxide semiconductor material. The nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Heng Wu, Julien Frougier, Ruilong Xie, Min Gyu Sung, Chen Zhang
  • Publication number: 20240391937
    Abstract: Disclosed are a compound as shown in formula (I), a stereoisomer, pharmaceutically acceptable salt, solvate, cocrystal or deuterated compound thereof, or a pharmaceutical composition containing same, and the use thereof as a PARP-1 inhibitor in the preparation of a drug for treating related diseases, wherein the definition of each group in formula (I) is as defined in the description.
    Type: Application
    Filed: September 30, 2022
    Publication date: November 28, 2024
    Inventors: Yao LI, Wenjing WANG, Lei CHEN, Peng KANG, Chao FU, Fengkai CHENG, Pingming TANG, Yan YU, Chen ZHANG, Pangke YAN
  • Patent number: 12154985
    Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: November 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Chen Zhang, Julien Frougier, Alexander Reznicek, Shogo Mochizuki
  • Publication number: 20240383874
    Abstract: Disclosed are a compound as represented by general formula (I) or a stereoisomer, deuterated compound, solvate, prodrug, metabolite, pharmaceutically acceptable salt or co-crystal thereof, and an intermediate thereof, and the use thereof in AR or AR splicing mutant-related diseases such as cancer.
    Type: Application
    Filed: November 24, 2021
    Publication date: November 21, 2024
    Inventors: Chen Zhang, Yuting Liao, Fei Ye, Pingming Tang, Xiaogang Chen, Yonghua Lu, Qiu Gao, Yao Li, Jia Ni, Pangke Yan