Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: An electronic device includes a substrate; and a coil structure disposed on the substrate. The coil structure is provided with a first conductor layer including a connection line; a second conductor layer including a plurality of line segments separated from each other; and a first insulation layer disposed between the first conductor layer and the second conductor layer, and provided with a plurality of first openings, wherein adjacent two of the plurality of line segments are electrically connected to the connection line through the plurality of first openings.

Abstract: An integrated circuit (IC) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. Each memory cell among the plurality of memory cells includes complementary field-effect transistor (CFET) devices.

Abstract: A memory macro includes an input/output (I/O) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the I/O circuit in the semiconductor wafer, wherein the first subset is positioned between the I/O circuit and the second subset, a first bit line coupled to the I/O circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the I/O circuit and extending on the other of the frontside or the backside along the first and second subsets. Each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.

Abstract: A boundary positioning device is adapted to pre-record a boundary of a to-be-worked area where an automatic mechanical equipment will be working. The boundary positioning device includes a machine frame, two wheels, a push rod, and a positioning module. When the boundary positioning device moves along the boundary, one of the wheels is located inside the to-be-worked area as an inner wheel, and the other one of the wheels is located outside the to-be-worked area as an outer wheel. The push rod extends rearwardly and upwardly from a rear side of the machine frame. The positioning module is disposed on the machine frame, and is spaced apart from the outer wheel by a distance same as a distance between a positioning unit and an outside-located wheel, which is located outside the to-be-worked area when the automatic mechanical equipment moves along the boundary of the automatic mechanical equipment.

Abstract: A multi-use monitoring system is disclosed, which comprises an electronic device, multiple sensor devices, multiple cameras, at least one wireless interface, and a remote electronic device. According to the present invention, the sensor devices are adopted for detecting multiple environmental parameters such as gas level, humidity and temperature, and the multiple cameras are controlled to acquire images from the poultry bred in a breeding environment. Therefore, after receiving the images and the environmental parameters from the electronic device, the remote electronic device can extract at least one poultry characteristic from the images, and then correlate the environmental parameters to the poultry characteristic(s). As a result, the remote electronic device can subsequently calculate an evaluation score according to the growth and/or health state of the poultry, such that the breeder can plan how to distribute the breeding resources for the poultry.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.

Abstract: A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

Abstract: Semiconductor devices including a first upper channel structure, a first intermediate structure below the first upper channel structure, a first lower channel structure below the first intermediate structure, and a voltage source connected to the first lower channel structure, in which the first upper channel structure, the first intermediate structure, and the first lower channel structure comprise a first vertical assembly that provides an electrical connection between the voltage source and the first upper channel structure.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: The invention provides an immersion fluid module including a tank, a heat exchanger, a condenser, and at least one pipe. The tank contains a first fluid. An electronic device is disposed in the tank and is at least partially immersed in the first fluid in a liquid state. The heat exchanger is disposed in the tank and is at least partially immersed in the first fluid in the liquid state. The condenser is disposed in the tank. The pipe connects the heat exchanger and the condenser. A second fluid is provided to the pipe, and a temperature of the second fluid is higher than a preset value. When an ambient temperature of the electronic device is lower than the preset value, the second fluid flows through the heat exchanger to raise the ambient temperature of the electronic device. The invention also provides a server system.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: A system and method for in-situ characterization of functional devices. The system comprises a vacuum chamber; a pump system coupled to the vacuum chamber for evacuation the vacuum chamber to near ultra high vacuum pressures of about 10?8 mbar or lower; a sample holder for a functional device based on nanostructured materials disposed inside the vacuum chamber and configured to provide electrical connection to the functional device for measuring electrical properties of the functional device; and a source system for exposing a surface/interface of the functional device to a modification species; whereby the system is configured to measure the electrical properties of the functional device in-situ upon the exposure to the modification species.

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

Abstract: A wireless communication device for communicating across a wireless communication channel includes a memory storing instructions and one or more processors coupled to the memory to execute the instructions stored in the memory. The instructions are configured to determine a plurality of channel estimation measurements corresponding to a plurality of PPDUs received from an additional wireless communication device; determine a plurality of position measurements using information about the transmission of the plurality of PPDUs, wherein the position measurement is a position of the additional wireless communication device relative to the wireless communication device; select a subset of the plurality of channel estimation measurements based on the plurality of position measurements; and determine a change in a state of the wireless communication channel based on the selected subset of the plurality of channel estimation measurements.

Abstract: System and methods are provided for detecting, tracking, and managing outages of transaction processors. An indication is received indicating a potential outage associated with a transaction processor computer configured to process transactions of an online retail website. The indication can be received from a threshold monitoring service and/or from a machine-learning detection system. A computing service can be initiated to confirm and track the outage over time. An outage may include a number of situations in which the transaction processor fails to process transactions according to a set of predefined processing parameters. If the outage spans a particular time period, the service can perform a number of remedial actions (e.g., notifying an administrator of the outage, etc.).

Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.