Patents by Inventor Cheng Chen

Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12366798
    Abstract: A lithography mask including a substrate, a phase shift layer on the substrate and an etch stop layer is provided. The phase shift layer is patterned and the substrate is protected from etching by the etch stop layer. The etch stop layer can be a material that is semi-transmissive to light used in photolithography processes or it can be transmissive to light used in photolithography processes.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20250234582
    Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.
    Type: Application
    Filed: March 31, 2025
    Publication date: July 17, 2025
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250234603
    Abstract: A semiconductor structure includes a plurality of nanosheets, a gate structure, an S/D structure, a stepped structure, and a sidewall spacer. The plurality of nanosheets is disposed over a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction. The gate structure is disposed over the substrate, wherein the gate structure is disposed between and surrounding the nanosheets. The S/D structure is disposed adjacent to the gate structure and the plurality of nanosheets. The stepped structure is disposed below the S/D structure, wherein the stepped structure overlaps at least one of the nanosheets along the first direction. The sidewall spacer is disposed between the stepped structure and the at least one of the nanosheets. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 17, 2025
    Inventors: TSUNG-HAN CHUANG, JUNG-HUNG CHANG, CHIA-CHENG TSAI, SHIH-CHENG CHEN, KUO-CHENG CHIANG, CHIH-HAO WANG
  • Publication number: 20250232985
    Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12362109
    Abstract: An electrical switch unit for use in controlling operation of an electrical device, the electrical switch unit including: an electrical switch unit housing for housing at least a pair of electrical switching contacts of the electrical switch unit, said electrical switch unit housing including a first housing member and a second housing member that are configured for attachment together at peripheral regions of the first and second housing members so as to cooperatively form an enclosed space for housing the pair of electrical switching contacts therein; an actuator member operably-connected with at least one of the pair of electrical switching contacts, the actuator being configured for movement relative inwardly and outwardly of an opening in the electrical switch unit housing so as to arrange the pair of electrical switching contacts into at least one of a closed configuration wherein power is able to be supplied from a power source to motor or other electrically-operable element of the electrical device vi
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 15, 2025
    Assignees: Defond Electech Co., Ltd., Defond Componets Limited
    Inventors: Wai Man Wong, Ming Leong Kong, Cheng Chen Nieh
  • Patent number: 12357434
    Abstract: A maxilla holder includes a base plate and a connecting member. One end of the connecting member is connected with the base plate which extends along a pre-designed occlusal plane while the other end of the connecting member includes at least two supporting portions. With the supporting portions abutting against the cranium, the base plate is positioned so that the maxilla is located in a pre-planned position once it is moved onto the base plate.
    Type: Grant
    Filed: August 23, 2024
    Date of Patent: July 15, 2025
    Inventor: Liang-Cheng Chen
  • Publication number: 20250224736
    Abstract: A boundary defining method implemented by a boundary defining system comprises: (A) obtaining a piece of positioning data that includes a path record and a signal status record, the path record indicating a circling path defining a circled area, the signal status record indicating one or more risky path sections in the circling path that meet a poor signal condition; (B) based on each risky path section indicated by the signal status record, determining an alternative path section corresponding to the risky path section and located within the circled area; and (C) based on at least the alternative path section(s), generating and outputting a piece of operating range data indicating an operating boundary, the operating boundary defining an operating area suitable for automatic movement of an autonomous mobile operation equipment, and that does not include the risky path section(s).
    Type: Application
    Filed: January 8, 2025
    Publication date: July 10, 2025
    Inventors: Chien-Tung CHEN, Chung-Hou WU, Chao-Cheng CHEN, Dien-Lin TSAI
  • Publication number: 20250216261
    Abstract: Methodology of various imaging modalities and engineering features are provided for multispectral soft tissue imaging architecture. The architectural designs comprise hardware of multiple ranges of wavelength for illumination and camera sensing and software for image acquisition, processing, feature abstraction, artificial intelligence-machine learning (AI-ML) analysis, visualization, and reporting. Embodiments of imaging hardware in a medical device can include a light source of multiple bands of wavelength of noncoherent and coherent light for broadband, narrowband, fluorescence, autofluorescence, Laser Speckle Imaging (LSI), Laser Doppler Imaging (LDI), tissue oxygenation imaging, and other variation of soft tissue imaging modalities.
    Type: Application
    Filed: January 3, 2025
    Publication date: July 3, 2025
    Inventors: Cheng Chen, Joffre Alvarez, Elizabeth Clarke, Megan Rosengarten, Phil Hodges
  • Publication number: 20250221027
    Abstract: A device includes a channel structure, a gate structure, a first source/drain epitaxial structure, and a second source/drain epitaxial structure. The channel layer is over a substrate and extends in a first direction. The gate structure covers the channel structure and extends in a second direction different from the first direction. The first source/drain structure and the second source/drain structure are on opposite sides of the channel structure. A void is contained in between the first source/drain structure and the substrate.
    Type: Application
    Filed: March 19, 2025
    Publication date: July 3, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Pi TSENG, De-Fang CHEN, Chao-Cheng CHEN
  • Patent number: 12347681
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Patent number: 12347051
    Abstract: A head-mountable display device includes a housing defining a front opening and a rear opening, a display screen disposed in the front opening, a display assembly disposed in the rear opening, a first securement strap coupled to the housing, the first securement strap including a first electronic component, a second securement strap coupled to the housing, the second securement strap including a second electronic component, and a securement band extending between and coupled to the first securement strap and the second securement strap.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: July 1, 2025
    Assignee: APPLE INC.
    Inventors: Michael J. Rockwell, Geoffrey Stahl, Thibaut Weise, Peter Kaufmann, Branko Petljanski, Jason L. Slupeiks, Tom Sengelaub, Kathrin Berkner Cieslicki, Yanghai Tsin, Hesam Najafi, Arthur Y. Zhang, Julian Hoenig, Julian Jaede, Jason C. Sauers, James W. Vandyke, Yoonhoo Jo, Forrest C. Wang, Cheng Chen, Graham B. Myhre, Fletcher R. Rothkopf, Marinus Meursing, Phil M. Hobson, Jan K. Quijalvo, Jia Tao, Ivan S. Maric, Jeremy C. Franklin, Wey-Jiun Lin, Bertrand Nepveu, Muhammad F. Hossain, William A. Sorrentino, III, Jonathan Ive, Alan C. Dye, Stephen O. Lemay
  • Publication number: 20250212479
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures formed over a substrate along a first direction, and a gate structure formed over the nanostructures along a second direction. The semiconductor structure includes an S/D structure formed adjacent to the gate structure, and a plurality of inner spacer layers between the gate structure and the S/D structure. The semiconductor structure includes a hard mask layer formed on the inner spacer layers, and a top surface of the hard mask layer is higher than a top surface of the S/D structure.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 26, 2025
    Inventors: Shih-Cheng CHEN, Wen-Ting LAN, Jung-Hung CHANG, Tsung-Han CHUANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG
  • Publication number: 20250209818
    Abstract: An intelligent meeting assistance system and a method for generating meeting minutes are provided. The intelligent meeting assistance system includes an image capturing device and an image analyzing device. The image capturing device is configured to capture an image displayed by an interactive device during a meeting. The image analyzing device is coupled to the image capturing device, and is configured to execute an image analysis process on the image to generate first meeting minutes that record image content.
    Type: Application
    Filed: July 9, 2024
    Publication date: June 26, 2025
    Inventors: CHIH-HAN YEN, Xiu-Lin Chao, TAO-CHENG CHEN
  • Patent number: 12341608
    Abstract: A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter, receiving an UNBOND set by a receiver, waking up a second transmitter by a LASM when the receiver receives the UNBOND set, transmitting a training sequence by the second transmitter, transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence, determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block, stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block, and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 24, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Patent number: 12342616
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: March 22, 2024
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chih-Hao Wang, Chien Ning Yao, Kuo-Cheng Chiang
  • Patent number: 12342587
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Chien Ning Yao, Shih-Cheng Chen, Jung-Hung Chang, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250200758
    Abstract: The present disclosure provides a position determining method, apparatus, electronic device and storage medium. The method includes: inputting a historical time queue and posture change information of a target object at a target point of time to a position estimation model to obtain an initial predicted position, wherein the historical time queue is used for storing historical position information of the target object at latest n historical points of time prior to the target point of time, and n is a preset positive integer not less than 2; and performing at least two iterative stages on the initial predicted position to obtain position information of the target object at the target point of time, wherein a positioning accuracy of any iterative stage is higher than a positioning accuracy of a previous iterative stage.
    Type: Application
    Filed: December 13, 2024
    Publication date: June 19, 2025
    Inventors: Panwang PAN, Jiao CHEN, Cheng CHEN, Yunlong LI, Meifeng XIAO
  • Patent number: 12335036
    Abstract: A method for link transitions in a Universal Serial Bus system includes transmitting a plurality of first RS-FEC blocks by a first transmitter of the USB system, transmitting a training sequence by a second transmitter of the USB system, determining number of sets in a first RS-FEC block which have been transmitted by the first transmitter when the second transmitter completes transmitting the training sequence, generating a specific pattern sequence according to the number of sets in the first RS-FEC block which have been transmitted by the first transmitter and a total number of sets in the first RS-FEC block, and transmitting the specific pattern sequence by the second transmitter.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 17, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Patent number: D1084895
    Type: Grant
    Filed: June 14, 2024
    Date of Patent: July 22, 2025
    Assignee: SITERWELL ELECTRONICS CO., LIMITED
    Inventors: Shixi You, Cheng Chen, Bin Liu, Zhenxiao Ding, Jiejun Wang
  • Patent number: D1080431
    Type: Grant
    Filed: May 16, 2024
    Date of Patent: June 24, 2025
    Assignee: SITERWELL ELECTRONICS CO., LIMITED
    Inventors: Shixi You, Cheng Chen, Haichun Wang