Patents by Inventor Cheng Chen

Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12347165
    Abstract: An accuracy measurement kit is provided and includes a marker, at least one light beam device, an image capture device, and a processing device. The marker is disposed on an autonomous mobile vehicle, and at least partially includes a reference pattern. The light beam device is configured to emit a light beam to the autonomous mobile vehicle located at a predetermined position so as to form a light spot on the marker. The processing device is configured to capture the light spot the marker on the autonomous mobile vehicle for generating a to-be-analyzed image. The processing device is configured to obtain an offset of the autonomous mobile vehicle in an X-axis direction and a Y-axis direction by calculating images of the to-be-analyzed image corresponding to the reference pattern and the light spot.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: July 1, 2025
    Assignee: AXIOMTEK CO., LTD.
    Inventors: Po-Cheng Chen, Kao-Pin Lin, Liang-Chin Wang
  • Patent number: 12347775
    Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lo-Heng Chang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 12349410
    Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Cheng-Lung Hung, Chi On Chui
  • Publication number: 20250210177
    Abstract: Electronic system and physiological monitoring method are provided. The electronic system includes a camera, an auxiliary feature sensor, and an accelerator. The camera is configured to take a facial image of a user. The auxiliary feature sensor is configured to sense an auxiliary feature of the user. The accelerator is configured to calculate an emotional status of the user according to the facial image. When it is determined that the emotional status meets a preset emotional status, the accelerator is configured to calculate an emotional level of the user by analyzing the auxiliary feature, and determine whether to issue an alert signal accordingly.
    Type: Application
    Filed: March 22, 2024
    Publication date: June 26, 2025
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Hung-Cheng Chen, Shu Jen Lin, Yi Tse Chen, Chiang Lung Lin
  • Publication number: 20250208358
    Abstract: An optical fiber accessory includes a front housing, a rear housing sleeve, and a loopback module. The front housing defines two insertion slots extending in a front-rear direction and spaced apart from each other in a first direction perpendicular to the front-rear direction, and two core slots being respectively in spatial communication with the insertion slots. The rear housing sleeve is sleeved on a rear end of the front housing and defines a receiving space in spatial communication with the core slots. The loopback module is disposed in the rear housing sleeve, and includes two ferrules fixed onto the rear housing sleeve, and an optical fiber loop having two ends respectively connected to the ferrules and disposed in the receiving space. The ferrules project toward the front housing in the front-rear direction and extend respectively into the core slots.
    Type: Application
    Filed: April 18, 2024
    Publication date: June 26, 2025
    Inventors: Hsien-Hsin HSU, Yu-Cheng CHEN, Jim LIN
  • Publication number: 20250212479
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures formed over a substrate along a first direction, and a gate structure formed over the nanostructures along a second direction. The semiconductor structure includes an S/D structure formed adjacent to the gate structure, and a plurality of inner spacer layers between the gate structure and the S/D structure. The semiconductor structure includes a hard mask layer formed on the inner spacer layers, and a top surface of the hard mask layer is higher than a top surface of the S/D structure.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 26, 2025
    Inventors: Shih-Cheng CHEN, Wen-Ting LAN, Jung-Hung CHANG, Tsung-Han CHUANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG
  • Publication number: 20250209818
    Abstract: An intelligent meeting assistance system and a method for generating meeting minutes are provided. The intelligent meeting assistance system includes an image capturing device and an image analyzing device. The image capturing device is configured to capture an image displayed by an interactive device during a meeting. The image analyzing device is coupled to the image capturing device, and is configured to execute an image analysis process on the image to generate first meeting minutes that record image content.
    Type: Application
    Filed: July 9, 2024
    Publication date: June 26, 2025
    Inventors: CHIH-HAN YEN, Xiu-Lin Chao, TAO-CHENG CHEN
  • Patent number: 12341608
    Abstract: A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter, receiving an UNBOND set by a receiver, waking up a second transmitter by a LASM when the receiver receives the UNBOND set, transmitting a training sequence by the second transmitter, transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence, determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block, stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block, and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 24, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Patent number: 12342587
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Chien Ning Yao, Shih-Cheng Chen, Jung-Hung Chang, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 12342616
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: March 22, 2024
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chih-Hao Wang, Chien Ning Yao, Kuo-Cheng Chiang
  • Patent number: 12340871
    Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hung Chang, Chia-Cheng Chen, Ching-Wei Wu, Cheng Hung Lee
  • Patent number: 12339126
    Abstract: A vehicular positioning method is provided for positioning a vehicle that is running on a road, where the road has a plurality of feature objects that have the same detectable feature and that are disposed along the road. The vehicle is provided with a system that counts a number of the feature objects the vehicle has passed by as the vehicle runs on the road, and that calculates a travelling distance the vehicle has traveled on the road based on the number counted thereby, an object length of the feature objects, and spacing between adjacent two of the feature objects. Then, the system displays an electronic map that shows the road and that indicates a position of the vehicle on the road based on the calculated travelling distance.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: June 24, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chia-Cheng Wang, Jyh-Cheng Chen
  • Patent number: 12342264
    Abstract: Provided herein is a method and apparatus for transmit parameter indication in support of Wireless Local Area Network (WLAN) sensing. The disclosure provides an apparatus, comprising: a Radio Frequency (RF) interface; and processor circuitry coupled with the RF interface, wherein the processor circuitry is to: decode an Information Element (IE) received from a WLAN device via the RF interface, wherein the IE is to indicate a transmit parameter for a transmission of a Physical layer Protocol Data Unit (PPDU) of the WLAN device; and perform WLAN sensing on the WLAN device based on the IE. Other embodiments may also be disclosed and claimed.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 24, 2025
    Assignee: INTEL CORPORATION
    Inventors: Cheng Chen, Carlos Cordeiro, Claudio Da Silva, Bahareh Sadeghi
  • Publication number: 20250200758
    Abstract: The present disclosure provides a position determining method, apparatus, electronic device and storage medium. The method includes: inputting a historical time queue and posture change information of a target object at a target point of time to a position estimation model to obtain an initial predicted position, wherein the historical time queue is used for storing historical position information of the target object at latest n historical points of time prior to the target point of time, and n is a preset positive integer not less than 2; and performing at least two iterative stages on the initial predicted position to obtain position information of the target object at the target point of time, wherein a positioning accuracy of any iterative stage is higher than a positioning accuracy of a previous iterative stage.
    Type: Application
    Filed: December 13, 2024
    Publication date: June 19, 2025
    Inventors: Panwang PAN, Jiao CHEN, Cheng CHEN, Yunlong LI, Meifeng XIAO
  • Publication number: 20250203902
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Application
    Filed: February 28, 2025
    Publication date: June 19, 2025
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20250204270
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Application
    Filed: March 2, 2025
    Publication date: June 19, 2025
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 12335036
    Abstract: A method for link transitions in a Universal Serial Bus system includes transmitting a plurality of first RS-FEC blocks by a first transmitter of the USB system, transmitting a training sequence by a second transmitter of the USB system, determining number of sets in a first RS-FEC block which have been transmitted by the first transmitter when the second transmitter completes transmitting the training sequence, generating a specific pattern sequence according to the number of sets in the first RS-FEC block which have been transmitted by the first transmitter and a total number of sets in the first RS-FEC block, and transmitting the specific pattern sequence by the second transmitter.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 17, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Patent number: 12334441
    Abstract: The present disclosure provides a semiconductor device and a semiconductor layout structure. In the semiconductor device, a guard ring of a first type is arranged on at least one side of a transistor of a second type, and a guard ring of a second type is arranged on at least one side of a transistor of a first type, such that a plurality of signal lines in a first metal layer in the semiconductor layout structure may be arranged between a first power source line and a first ground line. Furthermore, in a second metal layer, a plurality of second power source lines are connected to one first power source line, and a plurality of second ground lines are connected to one first ground line.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: June 17, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Li Tang, Cheng Chen, Yuxia Wang, Wei Jiang, Jing Xu
  • Patent number: 12336226
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Tsung-Han Chuang, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: D1080431
    Type: Grant
    Filed: May 16, 2024
    Date of Patent: June 24, 2025
    Assignee: SITERWELL ELECTRONICS CO., LIMITED
    Inventors: Shixi You, Cheng Chen, Haichun Wang