Patents by Inventor Cheng Chen

Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12314863
    Abstract: Approaches for determining quantization scale factors include generating a population of chromosomes. Each chromosome has multiple genes, and each gene specifies a scale factor associated with a layer of a machine learning model. The population of chromosomes are evaluated, and the evaluating includes, for each chromosome in the population, quantizing floating point weights and floating point values of a representative dataset using the scale factors of the chromosome to produce quantized weights and a quantized dataset in the memory arrangement, initiating processing of the quantized dataset using the quantized weights according to the machine learning model, and gauging a level of accuracy of results produced by the processing of the quantized dataset. Satisfaction of termination criteria is determined based the levels of accuracy associated with the chromosomes in the population.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: May 27, 2025
    Assignee: XILINX, INC.
    Inventors: Shaoxia Fang, Jiangsha Ma, Xi Wang, Junbin Wang, Cheng Chen, Taobo Wang
  • Patent number: 12315753
    Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12311354
    Abstract: Attachment devices for releasable coupling to a fluid dispensing device are provided. The attachment devices include a hollow body comprising a collar portion and a barrel portion extending from the collar portion. The barrel portion has an end portion having a closed end and at least one side opening. Longitudinally positioned along the exterior surface of the barrel is at least one rib branching upwards into two rib branches. When coupled to a fluid dispensing device, the assembly can be used to obtain a fluid sample. Thereafter the assembly can be used to dispense the fluid sample into an assay vessel so that the fluid sample can then be assayed. Methods for operating the attachment devices, and assemblies containing the attachment devices are also provided.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 27, 2025
    Assignee: FREDsense Technologies Corp.
    Inventors: Paul Mintchev, Cheng Chen, Lisa Oberding, Robert Mayall, Mhairi McDonald, Emily Hicks, Dylan Silver, Timothy Warrington
  • Patent number: 12317240
    Abstract: The disclosure provides techniques for a configuration of frequency domain aggregated (FA) physical layer protocol data unit (PPDU) for trigger based (TB) PPDUs. An apparatus for an access point (AP) includes a radio frequency (RF) interface; and processing circuitry coupled with the RF interface. The processing circuitry is configured to: encode a trigger frame to be transmitted via the RF interface to stations (STAs) communicatively connected with the AP, wherein the trigger frame includes signaling to indicate a configuration of frequency domain aggregated (FA) physical layer protocol data unit (PPDU) for at least two STAs; and decode an FA PPDU aggregated by composite trigger based (TB) PPDUs from the at least two STAs.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: May 27, 2025
    Assignee: INTEL CORPORATION
    Inventors: Xiaogang Chen, Cheng Chen, Po-Kai Huang, Thomas Kenney, Qinghua Li
  • Publication number: 20250169150
    Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Publication number: 20250156247
    Abstract: Embodiments of the present disclosure provide a data processing method, an electronic device, and a computer-readable storage medium. In a community division scenario, a community division algorithm is performed in parallel, through a plurality of threads and using fine-grained locks implemented based on atomic operation instructions, on a relationship network to realize community division.
    Type: Application
    Filed: August 12, 2024
    Publication date: May 15, 2025
    Inventors: Yongmin HU, Jing WANG, Cheng ZHAO, Yibo LIU, Cheng CHEN, Xiaoliang CONG, Chao LI
  • Publication number: 20250156428
    Abstract: An electronic device and a device function search method thereof are provided. The method is adapted for the electronic device having a plurality of functions and includes the following steps. A search query is obtained through an input device. A first semantic feature vector of the search query is generated by using a natural language model. Semantic similarity between the first semantic feature vector of the search query and at least one second semantic feature vector of each function is determined. A search result corresponding to the search query is determined according to the semantic similarity between the first semantic feature vector of the search query and the at least one second semantic feature vector of each of the functions. The search result includes at least one of the functions.
    Type: Application
    Filed: October 28, 2024
    Publication date: May 15, 2025
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yi-Nan Lee, Shih-Chieh Liao, Chin-Hao Chang, Shih-Chuan Chiu, Tzu-Hung Chuang, Chia-Hao Kang, Wei-Cheng Chen, Shin-Yi Huang, Tsung Huai Mou, Wen-Tsong Lu
  • Publication number: 20250159995
    Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Inventors: Hiroshi Osawa, Kyung-Wook Kim, Ming-Chin Hung, Shih Chang Chang, Yu-Cheng Chen
  • Patent number: 12300732
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Kuan-Ting Pan, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao, Kuo-Cheng Chiang
  • Patent number: 12301750
    Abstract: A method and a system for exercising policy control, a PCEF, and a PCRF are provided, which can solve the problem that no policy control can be exercised over application service flows without an application function (AF). The method includes of the following steps: a PCRF receiving information about an application event sent by a PCEF; and the PCRF generating a control policy for a service flow of the application according to the information about the application event, and delivering the control policy to the PCEF. In the present invention, the PCEF sends the obtained information about the application event to the PCRF, so that the PCRF can generate a control policy according to policy contexts including the information about the application event and the like, so as to exercise an effective policy control over the QoS guarantee, charging and gating of the service flow.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: May 13, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weihua Wei, Xinfa Wang, Cheng Chen, Shiyong Tan, Yan Li, Shibi Huang, Peng Zhao, Yuxin Mao
  • Patent number: 12300183
    Abstract: An electronic device such as a head-mounted device may have displays. The display may have regions of lower and higher resolution to reduce data bandwidth and power consumption for the display while preserving satisfactory image quality. Data lines may be shared by lower and higher resolution portions of a display or different portions of a display with different resolutions may be supplied with different numbers of data lines. Data line length may be varied in transition regions between lower resolution and higher resolution portions of a display to reduce visible discontinuities between the lower and higher resolution portions. The lower and higher resolution portions of the display may be dynamically adjusted using dynamically adjustable gate driver circuitry and dynamically adjustable data line driver circuitry.
    Type: Grant
    Filed: October 2, 2023
    Date of Patent: May 13, 2025
    Inventors: Cheng Chen, Jason C. Sauers, Fletcher R. Rothkopf, David W. Lum, Chun-Yao Huang, Enkhamgalan Dorjgotov, Graham B. Myhre, Bennett S. Wilburn, Paolo Sacchetto, Shih Chang Chang, Wonjae Choi, Cheuk Chi Lo
  • Patent number: 12300742
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 12298673
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: June 17, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-Cheng Ho, Chen-Shao Hsu
  • Publication number: 20250148637
    Abstract: The present disclosure provides a position determining method and apparatus, an electronic device and a storage medium. The method includes: determining whether a target object is located in a blind area of a camera at n historical moments of a historical time queue and a target moment; wherein the historical time queue is configured to store historical position information of the target object at latest n historical moments prior to the target moment, where n is a preset positive integer not less than 2; and in response to the target object being located outside the blind area of the camera at both of the n historical moments and the target moment, determining position information of the target object acquired by the camera at the target moment as the position information of the target object at the target moment.
    Type: Application
    Filed: November 1, 2024
    Publication date: May 8, 2025
    Inventors: Panwang PAN, Jiao CHEN, Cheng CHEN, Yunlong LI, Meifeng XIAO
  • Publication number: 20250150202
    Abstract: A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter, receiving an UNBOND set by a receiver, waking up a second transmitter by a LASM when the receiver receives the UNBOND set, transmitting a training sequence by the second transmitter, transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence, determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block, stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block, and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Publication number: 20250151509
    Abstract: Pixels in an organic light-emitting diode (OLED) display may be microcavity OLED pixels having optical cavities. The optical cavities may be defined by a partially transparent cathode layer and a reflective anode structure. The anode of the pixels may include both the reflective anode structure and a supplemental anode that is transparent and that is used to tune the thickness of the optical cavity for each pixel. Organic light-emitting diode layers may be formed over the pixels and may have a uniform thickness in each pixel in the display. Pixels may have a conductive spacer between a transparent anode portion and a reflective anode portion, without an intervening dielectric layer. The conductive spacer may be formed from a material such as titanium nitride that is compatible with both anode portions. The transparent anode portions may have varying thicknesses to control the thickness of the optical cavities of the pixels.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Gloria Wong, Jaein Choi, Sunggu Kang, Hairong Tang, Xiaodan Zhu, Wendi Chang, Kanuo C. Kustra, Rui Liu, Cheng Chen, Teruo Sasagawa, Wookyung Bae, Yusuke Fujino, Michael Slootsky
  • Publication number: 20250150201
    Abstract: A method for link transitions in a Universal Serial Bus system includes transmitting a plurality of first RS-FEC blocks by a first transmitter of the USB system, transmitting a training sequence by a second transmitter of the USB system, determining number of sets in a first RS-FEC block which have been transmitted by the first transmitter when the second transmitter completes transmitting the training sequence, generating a specific pattern sequence according to the number of sets in the first RS-FEC block which have been transmitted by the first transmitter and a total number of sets in the first RS-FEC block, and transmitting the specific pattern sequence by the second transmitter.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Publication number: 20250147332
    Abstract: Provided is a reticle pod with a detachable supporting mechanism, which is suitable for a dual pod, including an outer pod and an inner pod received therein, the inner pod including: a base, and at least a supporting mechanism, mounted on the base. The supporting mechanism includes: a supporting assembly, connected to a mounting interface of the base, the supporting assembly includes a seat, at least one limiting post, and a mounting hole, the at least one limiting post connects to the seat, the mounting hole penetrates the base and not a circular hole; and a supporting element, having a matching structure, so that the supporting element detachably received in the mounting hole.
    Type: Application
    Filed: October 16, 2024
    Publication date: May 8, 2025
    Inventors: Ming-Chien Chiu, Chia-Ho Chuang, Pin-Cheng Chen, Yen-Cheng Tu, Hsin-Min Hsueh
  • Publication number: 20250149431
    Abstract: A manufacturing method of an electronic package includes the following steps. A first interfacial dielectric layer is formed to cover sides of multiple first conductive vias and multiple second conductive vias. Multiple chips are directly bonded to the first and second conductive vias. A base dielectric layer is formed to fill a gap between the adjacent chips. A bridge element is directly bonded to the first conductive vias, such that the bridge element partially overlaps the adjacent chips respectively. A second interfacial dielectric layer and multiple third conductive vias are formed on the first interfacial dielectric layer and the bridge element. A redistribution circuit structure is formed on the second interfacial dielectric layer and the third conductive vias. Multiple conductive bumps are formed on the redistribution circuit structure. An electronic package is also provided.
    Type: Application
    Filed: July 8, 2024
    Publication date: May 8, 2025
    Applicant: VIA Technologies, Inc.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
  • Patent number: D1077248
    Type: Grant
    Filed: January 14, 2025
    Date of Patent: May 27, 2025
    Inventor: Cheng Chen