Abstract: A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second ring includes: a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions.

Abstract: A display including a display panel and a control module is disclosed. The display panel includes a plurality of same sub-pixel matrixes. Each sub-pixel matrix is formed by arranging a plurality of sub-pixels. The plurality of sub-pixels includes first sub-pixels corresponding to a first color, second sub-pixels corresponding to a second color, and third sub-pixels corresponding to a third color. The first sub-pixels, the second sub-pixels, and the third sub-pixels are all arranged on the display panel to form a shape of fold line having different folding lengths. The control module is coupled to the display panel and used to output a control signal to the display panel according to a display data to drive the plurality of sub-pixels on the display panel.

Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.

Abstract: A device includes a proportional-to-absolute-temperature (PTAT) current source having a bandgap reference voltage node, and a negative temperature dynamic load having an input terminal electrically connected to the bandgap reference voltage node.

Abstract: An electronic device for a wireless communication system is described. The electronic device comprises: a receiver configured to receive a modulated signal on a communication channel; and a processor, coupled to the receiver and configured to: process the received modulated signal; identify a communication channel characteristic based on the processed received modulated signal; select an equalizer having a first set of equalization coefficients based on the identified communication channel characteristic, wherein the first set of equalization coefficients is selected from a plurality of equalization coefficients, each of the plurality of equalization coefficients being associated with different communication channel characteristics; equalize the processed received modulated signal on the communication channel using the selected equalizer; and detect the equalized received modulated signal.

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: A memory architecture includes: a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; and a second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter, wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances. The first and second variable resistance dielectric layers are formed using a single process recipe. The first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.

Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.

Abstract: A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.

Abstract: A method for specific linkage to a glycoprotein includes obtaining a glycoprotein having a monoglycan or diglycan attached thereto; producing a reactive functional group on a sugar unit on the glycoprotein; and coupling a linker or a payload to the reactive functional group on the glycoprotein.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A spectrometer (100) and an optical input portion (32) thereof are disclosed. The optical input portion (32) comprises an assembly structure (322), and the assembly structure (322) is formed at a hole wall (321) of a through hole (3211) of the optical input portion (32). A light (L1) is incident into a dispersing element (2) of the spectrometer (100) along an optical path (13) after passing through the through hole (3211), and is dispersed by the dispersing element (2). The assembly structure (322) is used to be detachably assembled with an optical element (200). When the optical element (200) is assembled with the assembly structure (322), an optical axis of the optical element (200) is linked to the optical path (13). As a result, the light (L1) passing through the optical element (200) is incident to the dispersing element (2) along the optical axis and the optical path (13).

Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.

Abstract: An optical apparatus applied to ophthalmology detection is disclosed. The optical apparatus includes a first light source module, a second light source module, and an interference module. The first light source module is formed by a laser light source and lens units and used to emit a first light signal. The second light source module is formed by fiber units and lens units. The second light source module is coupled to the first light source module in series. The second light source module is used to receive a first light signal and emit a second light signal. The interference module is coupled to the second light source module and used to receive the second light signal and provide a first incident light and a second incident light to an object to be detected and a reference mirror respectively.

Abstract: A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.

Abstract: A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.

Abstract: An optical measuring apparatus and an operating method thereof are disclosed. The optical measuring apparatus includes a light source, a carrier chip, a light sensor, an analyzing chip and a display. Samples are uniformly distributed on the carrier chip. The light source emits sensing lights toward the carrier chip. The light sensor receives the sensing lights passing through the carrier chip at a plurality of times to obtain a plurality of images corresponding to the plurality of times respectively. The analyzing chip is coupled to the light sensor. The analyzing chip analyzes the object number and distribution variation with time in the sample according to the plurality of images corresponding to the plurality of times and estimates intrinsic characteristics of the object in the sample accordingly. The display is coupled to the analyzing chip. The display displays the intrinsic characteristics of the object in the sample.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: An optical measuring apparatus includes a first light source, a second light source and a switching unit. The first light source is used to emit a first light toward a first direction. The second light source is used to emit a second light toward a second direction. The switching unit selectively switches to a first mode or a second mode. When the switching unit switches to the first mode, it blocks the second light and let the first light emitted to an aiming region on eyeball to perform an optical aiming and determine an eye axis center position on the eyeball; when the switching unit switches to the second mode, the switching unit changes the second light from the second direction to the first direction to let the second light emitted to the eye axis center position on the eyeball to perform an optical measurement.