Abstract: A brake controller for spinner bikes has a frame body engaging a pair of connecting pieces, a shaft engaging a first block through a top end thereof and a second block through a bottom end thereof, and a magnetic encoder that has a PCB with coding circuit for detecting rotation of a magnet disposed under the second block. Thereby the brake controller controls two kinds of braking forces by a single button for spinner bikes.

Abstract: A memory architecture comprises a first memory macro comprising a first plurality of memory cells, a second memory macro comprising a second plurality of memory cells, and a control logic coupled to the first and second memory macros. The control logic is configured to write a logical state to each of the first and second pluralities of memory cells by using first and second signal levels, respectively, thereby causing the first and second memory macros to be used in first and second applications, respectively, the first and second signal levels being different and the first and second applications being different. The first and second memory macros are formed on a single chip, and wherein the first and second pluralities of the memory cells comprise a variable resistance dielectric layer formed using a single process recipe.

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

Abstract: An electronic device for a wireless communication system is described. The electronic device comprises: a receiver configured to receive a modulated signal on a communication channel; and a processor, coupled to the receiver and configured to: process the received modulated signal; identify a communication channel characteristic based on the processed received modulated signal; select an equalizer having a first set of equalization coefficients based on the identified communication channel characteristic, wherein the first set of equalization coefficients is selected from a plurality of equalization coefficients, each of the plurality of equalization coefficients being associated with different communication channel characteristics; equalize the processed received modulated signal on the communication channel using the selected equalizer; and detect the equalized received modulated signal.

Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.

Abstract: A device is disclosed that includes a driver, a sinker and a memory column. The memory column includes a plurality of resistive memory cells each being electrically connected between the driver and the sinker through a first line and a second line. When one of the resistive memory cells is conducted, at least one of the driver and the sinker is configured to be controlled to have a resistance depending on a row location of the conducted resistive memory cell in the memory column.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.

Abstract: A noise-reducing fan system, comprising a motor, a fan body, a plurality of magnetic-inducing elements, a magnetic field generator and a noise-reducing sound source device, is provided. Here, the fan body is mounted on the motor. The fan body comprises a plurality of blades, on which the plurality of magnetic-inducing elements are disposed, respectively. The magnetic field generator, which may generate a magnetic field, is employed for driving the plurality of magnetic-inducing elements to vibrate the plurality of blades and generate a vibration sound, so that at least one portion of the noise emitted from the fan body as rotating may be counterbalanced. The noise-reducing sound source device is disposed on a predetermined position and may send out a noise-reducing sound, so that the noise-reducing sound may counterbalance at least the other portion of the noise emitted from the fan body as rotating.

Abstract: The present invention relates to an antibody or antigen-binding fragment thereof that bind human vascular endothelial growth factor receptor 2 (VEGFR-2). The present invention also relates to a method for inhibiting VEGFR-2-mediated signaling in a subject in need, a method for treating diseases and/or disorders caused by or related to VEGFR-2 activity and/or signaling in a subject afflicted with the diseases and disorders, a method for treating tumor in a subject afflicted with the tumor, a method for inhibiting cell proliferation of endothelial cells in a subject in need, and a method for detecting human vascular endothelial growth factor receptor in a sample.

Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.

Abstract: An implementation of the invention is directed to a passive device cell having a substrate layer, and intermediary layer formed above the substrate layer, and a passive device formed above the intermediary layer. The intermediary layer includes a plurality of LC resonators and a plurality of segmented conductive lines, wherein the plurality of segmented conductive lines are disposed between the plurality of LC resonators.

Abstract: A secure payment device having first and second modes is provided. In the second mode, a payment procedure is activated to receive data of a payment member for a secure payment. The secure payment device includes a touch screen group, a payment unit, a central processing unit and a secure microprocessor unit. The touch screen group displays an operation interface and a secure payment interface. In the first mode, the operation interface receives a first operation instruction via the operation interface. In the second mode, the secure payment interface obtains the data of the payment member by the payment unit, receive the second operation instruction via the secure payment interface, and activate the payment function based on a comparing result of the authentication information and the data of the payment member. A secure payment method for the aforementioned secure payment device is also provided.

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

Abstract: A device is disclosed that includes a driver, a sinker, a memory column, a reference column, a reference resistor and a sensing unit. At least one of the driver and the sinker has a trimmable resistance. For write operation, one of resistive memory cells is conducted based on a row location in the memory column thereof, the driver provides a write current flowing therethrough and the trimmable resistance is trimmed based on the row location. For read operation, the sensing unit senses a read current of the memory column and a reference current of the reference column and the reference resistor when one of the resistive memory cells and a positionally corresponding one of the reference bit cells are conducted.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: The present disclosure provides a semiconductor structure Which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.

Abstract: A circuit for programming a memory cell having a programmable resistance includes a switch. The circuit is configured to apply a programming voltage to the memory cell when the switch is in a first state. The circuit is configured to apply a programming current to the memory cell when the switch is in a second state. The resistance of the memory cell changes from a first resistance state to a second resistance state based on the application of the programming voltage or the programming current to the memory cell.

Abstract: Systems, methods, architectures, and computer program products for linking multiple devices are disclosed. In an example for linking a mobile device with a desktop device, an identifier of a mobile device can be received from a desktop computer. The identifier can be used to send a link to the mobile device. When the link is accessed, a code and a channel are generated. The mobile device is connected to the channel and the code is provided to the mobile device. The code is entered at the desktop device and the desktop device is connected to the channel responsive to the code being validated, thereby linking the desktop and mobile devices.