Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.

Abstract: A learning system with augmented reality is provided. The learning system includes a cloud server recording an operation history of a learner and providing feedback messages, and a mobile device having an image-capturing module capturing an image of a substantial object. Also, the learning system comprises an object database storing a simulated object corresponding to the substantial object, an identification module identifying the image and generating image information, and a processing module which receives and analyzes the image information, obtains the simulated object from the object database according to analyzing results, and displays the simulated object on a display interface of the mobile device. The learning system allows learner to operate simulated object operation instructions on the display interface or directly operate the substantial object to control a display status of the simulated object, and the operation history of learner is transmitted to the cloud server.

Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.

Abstract: Circuits and methods for detecting write operation and limiting cell current in resistive random access memory (RRAM or ReRAM) cells are provided. RRAM cells can include a select transistor and a programmable resistor. Current can flow through the programmable resistor responsive to word line voltage VWL applied to the gate of the select transistor and a bit line voltage VBL applied to the source of the select transistor. Responsive to the current, the programmable resistor can change between relatively high and low resistances (“SET”), or between relatively low and high resistances (“RESET”). It can be desirable to accurately characterize the resistance of the programmable resistor, that is, to accurately detect write operations such as SET or RESET. Additionally, it can be undesirable for the current to exceed a certain value (“over-SET”). The present circuits and methods can facilitate detecting write operations or limiting current, or both, in an RRAM cell.

Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.

Abstract: An optical device for corneal measuring includes a light source module, a first optical module, a second optical module including a reference mirror, a light splitter and an image analysis unit. The light of the light source module is transmitted to the first and second optical modules through the light splitter. The light is transmitted to a cornea through the light splitter and the first optical module and reflected by the cornea to form a first light, the light is transmitted to the reference mirror through the light splitter and reflected by the reference mirror to form a second light. The first and second lights are transmitted to the light splitter and the image analysis unit. The reference mirror moves along a first direction, and when the first light and the second light interfere with each other, a relative optical path length is obtained.

Abstract: A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.

Abstract: A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed in a top portion of the semiconductor substrate, having a second dopant type opposite to the first conductivity type, and an interconnect element formed over the semiconductor substrate, covering the first doping regions.

Abstract: A device includes an amplifier stage, a source follower, a resistive device, and a transistor. The source follower has an input terminal electrically coupled to an internal node of the amplifier stage, and an output terminal electrically coupled to an input terminal of the amplifier stage and an output terminal of the device. The resistive device has a first terminal electrically coupled to the output terminal of the device. The transistor is electrically coupled to a second terminal of the resistive device and the amplifier stage.

Abstract: An electric conduction heat dissipation substrate includes a ceramic substrate, and a seed layer, and a buffering material layer and a copper circuit layer formed thereon in order. The buffering material layer has a coefficient of thermal expansion between those of the ceramic substrate and the copper circuit layer. Moreover, the buffering material layer is composed of alloy material and ceramic material or composed of metal material and ceramic material.

Abstract: An optical device for corneal measuring includes a light source module, a first optical module, a second optical module including a reference mirror, a light splitter and an image analysis unit. The light of the light source module is transmitted to the first and second optical modules through the light splitter. The light is transmitted to a cornea through the light splitter and the first optical module and reflected by the cornea to form a first light, the light is transmitted to the reference mirror through the light splitter and reflected by the reference mirror to form a second light. The first and second lights are transmitted to the light splitter and the image analysis unit. The reference mirror moves along a first direction, and when the first light and the second light interfere with each other, a relative optical path length is obtained.

Abstract: A fitness transmission apparatus including an information carrying assembly and an information reading assembly is provided. The information carrying assembly is disposed on a fitness equipment. The information carrying assembly is configured to record a weight information of the fitness equipment by using a plurality of information record combinations. The information reading assembly is disposed on the fitness equipment. The information reading assembly is configured to read the weight information in a predetermined manner based on types of the information record combinations. The information reading assembly is paired to the information carrying assembly in the predetermined manner to read the weight information. The information reading assembly transmits the read weight information to an electronic device. Furthermore, an information processing method is also provided.

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

Abstract: Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.

Abstract: A device includes a signaling interface to receive OFDM signaling for an OFDM channel from a plurality of transmit nodes and an OFDM receiver process the OFDM signaling. The device further includes a channel allocation module to determine, for each transmit node, a corresponding SNR for each of a plurality of subchannels of the channel and to allocate, to each transmit node of the plurality of transmit nodes, a corresponding subset of subchannels of the plurality of subchannels. The channel allocation module further is to select, for each subset of subchannels, one or more subchannels for use as pilots by the corresponding transmit node based on the SNRs of the subchannels in the subset. The device further includes an OFDM transmitter to transmit configuration information to the plurality of transmit nodes, the configuration information representing the allocation of the subchannels and the selection of subchannels for use as pilots.

Abstract: A device includes a signaling interface to receive OFDM signaling for an OFDM channel from multiple transmit nodes, an OFDM receiver to process the OFDM signaling, and a channel allocation module. The channel allocation module allocates subchannels of the channel among transmit nodes by: determining, for each transmit node, a corresponding SNR for each of the subchannels; assigning to each transmit node a corresponding subset of buckets of a set of buckets, the number of buckets in the subset based on a data rate requirement of the transmit node; distributing subchannels among the buckets based on the SNRs of the subchannels; and, for each transmit node, allocating to the transmit node the subchannels distributed to the subset of buckets assigned to the transmit node. The device further includes an OFDM transmitter to transmit configuration information to the transmit nodes, the configuration information representing the allocation of the subchannels.

Abstract: A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror current that mirrors the write current, and inhibiting application of a write voltage to the memory cell of the memory based on the mirror current. A device that performs the method is also disclosed. A memory that includes the device is also disclosed.

Abstract: The present invention related to a test strip and a method for humidity detection. The test strip comprises two humidity detecting materials for detecting humidity change and one of the humidity detecting materials is exposed to outer environment. Detect the two humidity changes to obtain a ratio that is used for comparing with a value and then it can prevent from exceeding a predetermined humidity value, and whereby the test strip and the method could achieve the goal of simple humidity detection.