Patents by Inventor Cheng Chuang

Cheng Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170262117
    Abstract: A touch panel assembly includes a touch panel, a flexible circuit board, an input element and a light emitting element. The touch panel includes sensing series and pads. The pads are disposed on bonding regions of the touch panel and electrically connected to the sensing series. The flexible circuit board includes bonding portions and a light guide portion. Each bonding portion is disposed at the bonding region and includes terminals electrically connecting the pads. The light guide portion includes a connecting portion connecting the corresponding bonding portion and an extending portion connecting the connecting portion and extended away from the touch panel. The input element is located right above the extending portion. The light emitting element is disposed at a light incident side of the light guide portion.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 14, 2017
    Inventors: Po-Chin Huang, Shih-Po Chien, Yu-Jing Liao, I-Cheng Chuang
  • Patent number: 9761568
    Abstract: A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 12, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Chia-Wei Chang, Kuo-Ting Lin, Yong-Cheng Chuang
  • Patent number: 9743486
    Abstract: An electronic device including a body and a light source module is provided. The body has a side on which an unstable display is disposed and another side on which a bi-stable display is disposed. The light source module is arranged inside the body and configured to provide a light source to one or none of the unstable display and the bi-stable display.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: August 22, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Kai-Cheng Chuang, Cheng-Hao Lee
  • Patent number: 9728352
    Abstract: A switch structure and an electronic device using the same are provided. The electronic device has a casing, and the switch structure is disposed at an inner side of the key portion of the casing. The switch structure includes an elastic member, a force transmission member and a strain sensor. The elastic member is connected to the casing. The force transmission member is located inside the casing. The strain sensor is disposed on the elastic member, and the strain sensor and the force transmission member are disposed are two opposite sides of the elastic member respectively. The elastic member is configured to be deformed by the force transmission member when an external force is applied to an outside of the key portion.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: August 8, 2017
    Assignee: HTC Corporation
    Inventors: I-Cheng Chuang, Yu-Jing Liao, Ying-Yen Cheng, Chih-Wei Tu, Hung-Wen Lin
  • Publication number: 20170212602
    Abstract: A virtual reality clamshell computing device includes a number of projection devices to project a three-dimensional image, a number of infrared OR illumination devices to illuminate a users hand, a number of IR sensors to detect IR wavelengths reflected off of the users hand, a processor, and a memory. The memory includes executable code that, when executed by the processor, extracts coordinate location data from the detected IR wavelengths reflected off of the users hand, interprets the coordinate location as a number of gestures performed by the user, and manipulates the display of the three-dimensional image based on the interpreted gestures.
    Type: Application
    Filed: July 31, 2014
    Publication date: July 27, 2017
    Inventors: Joe HSU, Yu-Hung LI, Hao-Cheng CHUANG
  • Patent number: 9716080
    Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer is disposed on the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the dummy spacer are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and the surface of the dummy spacer but exposes the polished cross-sectional surfaces. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: July 25, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Yong-Cheng Chuang, Chia-Wei Chang
  • Publication number: 20170194231
    Abstract: Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure.
    Type: Application
    Filed: December 20, 2016
    Publication date: July 6, 2017
    Inventor: Yong-Cheng CHUANG
  • Patent number: 9699049
    Abstract: In an example embodiment, clusters of nodes in a network are monitored. Then the monitored data may be stored in an open time-series database. Data from the open time-series database is collected and labeled it as training data. Then a model is built through machine learning using the training data. Additional data is retrieved from the open time-series database. The additional data is left as unlabeled. Anomalies in the unlabeled data are computed using the model, producing prediction outcomes and metrics. Finally, the prediction outcomes and the network.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 4, 2017
    Assignee: eBay Inc.
    Inventors: Chaitali Gupta, Mayank Bansal, Tzu-Cheng Chuang, Ranjan Sinha, Sami Ben-Romdhane
  • Publication number: 20170186737
    Abstract: A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 29, 2017
    Inventors: Li-Chih FANG, Chia-Wei CHANG, Kuo-Ting LIN, Yong-Cheng CHUANG
  • Patent number: 9690407
    Abstract: A cover plate used for an electronic device is provided. The cover plate includes a plate and a conductive layer. The plate has two surfaces opposite to each other and a lateral surface connected between the two surfaces. The lateral surface of the plate is framed by the conductive layer which is electrically connected to a ground end of the electronic device. The disclosure further provides an electronic device including the cover plate and a main body. The main body is disposed within the electronic device and electrically connected to the conductive layer.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: June 27, 2017
    Assignee: HTC Corporation
    Inventors: Shih-Po Chien, Yi-Ting Liu, Yu-Jing Liao, I-Cheng Chuang, Chia-Huan Chang
  • Patent number: 9685805
    Abstract: An assembled electronic apparatus and a control method thereof are provided. The assembled electronic apparatus includes a first body and a second body. A second processor shares a partial content of a sensing record generated by a sensing module through a second information sharing module. The first body and the second body are connected with each other through the first connector and the second connector. After being connected with each other, a message is transmitted by one of the first processor and the second processor to another one of the first processor and the second processor, so that a function is executed by the another one of the first processor and the second processor through the corresponding first processor or the corresponding second processor according to the message. The first processor shares a content of the sensing record generated by the sensing module through a first information sharing module.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: June 20, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Kai-Yi Chen, Hsiu-Hang LIn, Ching-Wen Sun, Pin-Yu Chou, Yu-Tzu Hsu, Chia-Ni Chen, Wei-Cheng Chuang, Ming-Feng Liu
  • Publication number: 20170167914
    Abstract: An optical sensing module capable of providing a multi-directional optical sensing function teaches that the optical sensing module can be fixed on a circuit board via a bridging medium. The optical sensing module includes a supporter, a photosensitive component and a connecting component. The supporter includes a base and several lateral portions. The lateral portions are bent from edges of the base to form an accommodating space. The photosensitive component is disposed inside the accommodating space to receive an optical signal passing into an opening of the accommodating space. The connecting component is disposed on the supporter and includes a conductive terminal. The supporter is connected with the bridging material via the conductive terminal to stand on the circuit board by one of a plurality of sensing directions.
    Type: Application
    Filed: July 24, 2016
    Publication date: June 15, 2017
    Inventors: Chi-Chih Shen, Jen-Yu Chen, Yen-Hsin Chen, Kuo-Hsiung Li, Jui-Cheng Chuang
  • Patent number: 9674908
    Abstract: A secondary-side bucking and current-stabilizing flyback power converter adopts a dual-stage isolated circuit architecture and outputs a constant output current to drive a low-power LED module, and its primary stage adopts a flyback circuit architecture with a primary regulated voltage, and its secondary stage adopts of a buck circuit architecture of the current stabilizer, so that after the primary stage converts the constant voltage, the current stabilizer senses the load effect of the output current at the LED module to regulate the output cycle and maintain the total output of the output current constant and reduce the ripple amplitude, so as to achieve a non-strobe output result and improve the illumination effect of the LED module.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 6, 2017
    Assignee: Unity Opto Technology Co., Ltd.
    Inventors: Chih-Hsien Wu, Wei Chang, Kai-Cheng Chuang, Sheng-Wei Chen, Che-Hao Kuo
  • Patent number: 9670016
    Abstract: A transmission device of automatic document feeder includes a pickup roller assembly, a paper-feed roller assembly, a paper-out roller assembly, a pickup gear assembly for driving the pickup roller assembly, a first transmission gear assembly, a second transmission gear assembly, a drive gear assembly and a motor. The paper-feed roller assembly includes a paper-feed shaft. The paper-out roller assembly includes a paper-out shaft. The first transmission gear assembly includes a first one-way gear and a second one-way gear. The motor bidirectionally drives the drive gear assembly. The motor drives the drive gear assembly to drive the first one-way gear together with the second transmission gear assembly or the second one-way gear together with the second transmission gear assembly to drive the paper-out shaft and the paper-feed shaft to unidirectionally rotate towards the same direction.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 6, 2017
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Hung Ming Chou, Chi Cheng Chuang
  • Patent number: 9673178
    Abstract: Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 6, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Hsiang Yuan, Chia-Wei Chang, Kuo-Ting Lin, Yong-Cheng Chuang
  • Publication number: 20170155744
    Abstract: A network packet management server, a network packet management method and a computer readable medium thereof are provided. The network packet management server runs a packet management program which includes a graphical user interface (GUI) to execute the packet management method. The network packet management server receives internet of things (IoT) device information through a network, generates header field analysis information in response to an operation on the GUI, and generates a packet processing prediction message according to the header field analysis information and the IoT device information. Accordingly, the network packet management server is able to generate at least one control message based on the packet processing prediction message so as to send the at least one control message to at least one of a network control device and a gateway via the network.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 1, 2017
    Inventors: Chao-Hsien LEE, Ying-Hsun LAI, Yu-Hsiu LIN, Chi-Cheng CHUANG
  • Patent number: 9659911
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer (RDL), at least one first die, a plurality of conductive terminals and solder balls, a first encapsulant, a plurality of second dies, and a second encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first die and the conductive terminals are electrically connected to the RDL and are located on the first surface of the RDL. The first encapsulant encapsulates the first die and the conductive terminals. The first encapsulant exposes part of the conductive terminals. The solder balls are electrically connected to the conductive terminals and are located over the conductive terminals exposed by the first encapsulant. The second dies are electrically connected to the RDL and are located on the second surface of the RDL. The second encapsulant encapsulates the second dies.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 23, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Wei Chang, Li-Chih Fang, Kuo-Ting Lin, Yong-Cheng Chuang
  • Patent number: 9659886
    Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: May 23, 2017
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Hung-Mo Wu, Ying-Cheng Chuang
  • Publication number: 20170140077
    Abstract: The method for assessing efficiency in power production of a power generation system comprises: receiving meteorological data and environmental sensor data from potential power generation sites, wherein the meteorological data comprise weather-related factors, and the environmental sensor data comprise operation parameters of a power generation system; establishing a first-relationship model associated with the meteorological data from the potential power generation sites and weather-related factors from the assessed target site; receiving operation parameter of the power generation system at the potential power generation sites, and establishing a second-relationship model associated with the weather-related factor and the operation parameter; and receiving weather-related factors from the assessed target site, and estimating operation parameter of the power generation systems from the assessed target site according to the weather-related factor, the first-relationship model, and the second-relationship mode
    Type: Application
    Filed: December 2, 2015
    Publication date: May 18, 2017
    Inventors: YU-HSIU LIN, YING-HSUN LAI, CHI-CHENG CHUANG
  • Patent number: D794866
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 15, 2017
    Assignee: Unity Opto Technology Co., Ltd.
    Inventors: Chih-Hsien Wu, Wei Chang, Kai-Cheng Chuang, Yi-Shu Chen, Hsin-Chieh Liao, Sen-Yuh Tsai, Ching-Ping Tseng