Abstract: Transparent conductive electrodes of a touch panel including a plurality of first electrode patterns are provided. An edge of each of the first electrode patterns has a first outer etching line and a second outer etching line that are parallel to each other. A plurality of first inner etching lines are formed between any two of the adjacent first electrode patterns. A first distance is defined between each of the first outer etching lines and each of the second outer etching lines. A second distance is defined between each of the second outer etching lines and each of the first inner etching lines adjacent and parallel thereto. The first distance is less than the second distance, and the second distance is less than or equal to 15 times the first distance. The first distance is less than a distance between any two of the first inner etching lines.

Abstract: There is provided an optical sensor package including a substrate, a base layer, an optical detection region, a light source and a light blocking wall. The base layer is arranged on the substrate. The light detection region and the light source are arranged on the base layer. The light blocking wall is arranged on the base layer, and located between the light detection region and the light source to block light directly propagating from the light source to the light detection region.

Abstract: Transparent conductive electrodes of a touch panel including a plurality of first electrode patterns are provided. An edge of each of the first electrode patterns has a first outer etching line and a second outer etching line that are parallel to each other. A plurality of first inner etching lines are formed between any two of the adjacent first electrode patterns. A first distance is defined between each of the first outer etching lines and each of the second outer etching lines. A second distance is defined between each of the second outer etching lines and each of the first inner etching lines adjacent and parallel thereto. The first distance is less than the second distance, and the second distance is less than or equal to 15 times the first distance. The first distance is less than a distance between any two of the first inner etching lines.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

Abstract: A method of manufacturing a semiconductor structure includes: etching a substrate according to a hard mask to form a plurality of trenches in the substrate; performing a nitridation treatment on the trenches of the substrate; filling the trenches of the substrate with a flowable isolation material; and solidifying the flowable isolation material to form an isolation material. A semiconductor structure manufactured by the method is also provided.

Abstract: A method of manufacturing a semiconductor structure includes the following operations. A buffer layer is formed over a substrate. A first top hard mask is formed on the buffer layer, in which the first top hard mask has a first trench to expose a first portion of the buffer layer. A spacer layer is formed to cover a sidewall of the first trench and an upper surface of the first top hard mask and the first portion of the buffer layer to form a second trench over the first portion. The top portion and the bottom portion are etched to form a thinned top portion and a thinned bottom portion. A second top hard mask is formed in the second trench. The thinned top portion and the vertical portion of the spacer layer are removed.

Abstract: A three-dimensional sensing module includes a touch pressure sensing structure. The touch pressure sensing structure includes a first functional spacer layer, a first light-transmitting electrode layer coated on the first functional spacer layer, a second functional spacer layer coated on the first light-transmitting electrode layer, a second light-transmitting electrode layer coated on the second functional spacer layer, and a third functional spacer layer coated on the second light-transmitting electrode layer. Resistivities of the first, second, and third functional spacer layers are greater than resistivities of the first and second light-transmitting electrode layers.

Abstract: Provided herein are devices and systems comprising an illumination module configured to provide a source light to an optical interference module, which converts the source light to a line of light and processes light signal; an interference objective module, which handles light from the optical interference module and processes light signal generated from a sample; a two-dimensional camera configured to receive a backscattered interference signal from the sample, and a data processing module which processes the interference signal into an image.

Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Abstract: The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer.

Abstract: A method for forming a semiconductor structure includes: providing a structure including a substrate and a target layer disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of linear fin features within the central area in which the linear fin features are substantially parallel to each other and include edge imbalance portions; and removing the edge imbalance portions of the linear fin features to obtain linear uniform fin features.

Abstract: A method of manufacturing a semiconductor structure includes: etching a substrate according to a hard mask to form a plurality of trenches in the substrate; performing a nitridation treatment on the trenches of the substrate; filling the trenches of the substrate with a flowable isolation material; and solidifying the flowable isolation material to form an isolation material. A semiconductor structure manufactured by the method is also provided.

Abstract: A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

Abstract: A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Abstract: The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.

Abstract: A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Abstract: A detection method of a three-dimensional touch module includes: step S1, providing an input signal to a transmitting electrode layer; step S2, outputting a first output signal and transmitting the first output signal to a control module by a two-dimensional inputting assembly, and outputting a second output signal and transmitting the second output signal to the control module by a pressure sensing assembly; and step S3, determining, by the control module, a touch position according to the first output signal and a pressure value according to the second output signal. A three-dimensional touch module includes: a cover plate; a two-dimensional inputting assembly disposed under the cover plate and configured to output a first output signal; a pressure sensing assembly disposed under the cover plate and configured to output a second output signal; and a transmitting electrode layer disposed between the two-dimensional inputting assembly and the pressure sensing assembly.

Abstract: An electronic apparatus includes a flexible cover plate, a force sensing module, a touch display module, and a metal thin plate. The force sensing module includes a flexible electrode and a flexible force-sensitive composite layer. The flexible force-sensitive composite layer includes at least one flexible electrode layer and at least one functional spacer layer. The flexible electrode layer has a first resistivity. The functional spacer layer has a second resistivity greater than the first resistivity. The flexible electrode layer and the functional spacer layer are disposed under the flexible electrode. The touch display module is disposed between the flexible cover plate and the force sensing module and includes an organic light emitting display unit and a touch sensing layer. The metal thin plate is disposed under the force sensing module and serves as a contact electrode of the force sensing module.