Abstract: Certain aspects of the present disclosure provide methods and apparatus for processing an input signal. One example apparatus is a circuit that generally includes an amplifier, comprising a first transistor and a second transistor connected in cascode with the first transistor; a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.

Abstract: An active balun uses two inverters to produce a differential output from a single-ended input. A current source supplies current to both inverters and a current sink sinks current from both inverters. The inverters include bias resistors coupled between their inputs and outputs. A coupling capacitor couples the output of the first inverter to the input of the first inverter. Values of the bias resistors and the coupling capacitor may selected to assure stability of the active balun. The values may be programmable, for example, based on a desired operating frequency. The current source may be biased by a common-mode feedback circuit based on the common-mode voltage of the differential output.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for processing an input signal. One example apparatus is a circuit that generally includes an amplifier, comprising a first transistor and a second transistor connected in cascode with the first transistor; a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.

Abstract: An active balun uses two inverters to produce a differential output from a single-ended input. A current source supplies current to both inverters and a current sink sinks current from both inverters. The inverters include bias resistors coupled between their inputs and outputs. A coupling capacitor couples the output of the first inverter to the input of the first inverter. Values of the bias resistors and the coupling capacitor may selected to assure stability of the active balun. The values may be programmable, for example, based on a desired operating frequency. The current source may be biased by a common-mode feedback circuit based on the common-mode voltage of the differential output.

Abstract: An amplifier includes a gain transistor including a control terminal to receive an input signal. A degeneration inductor is coupled between the first terminal of the gain transistor and ground. A shunt inductor and a capacitor are coupled in series between the control terminal of the gain transistor and ground, and form a filter to attenuate frequencies of the input signal within a frequency range. The degeneration inductor and the shunt inductor form a transformer to provide impedance matching.

Abstract: Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a first periodic signal; a second path having a second frequency divider configured to generate a second divided signal from a second periodic signal; a phase detector configured to compare phases of a first sensing signal based on the first divided signal and a second sensing signal based on the second divided signal and to generate a first trigger signal if the first and second sensing signals are out-of-phase; and a first pulse suppressor configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal.

Abstract: A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.

Abstract: An apparatus includes a first bias circuit configured to generate a first current that varies with temperature according to a first slope. The apparatus also includes a second bias circuit configured to generate a second current that varies with temperature according to a second slope. The apparatus further includes a low noise amplifier including a transconductance stage that is responsive to an output of the first bias circuit. The apparatus also includes a load coupled to an output of the low noise amplifier and responsive to an output of the second bias circuit.

Abstract: A power amplifier bias circuit having high dynamic range and low memory is disclosed. In an exemplary embodiment, an apparatus includes an output stage configured to generate a biased RF signal based on a first DC signal and a filtered signal. The apparatus also includes a low pass filter configured to filter the biased RF signal to generate the filtered signal.

Abstract: A method and apparatus are disclosed for a configurable amplifier. When operating in a first operating mode, the configurable amplifier may amplify a communication signal and may cancel or attenuate a second harmonic component associated with the communication signal. When operating in a second operating mode, the configurable amplifier may amplify the communication signal without cancelling or attenuating the second harmonic component associated with the communication signal.

Abstract: A circuit for performing a residual side band calibration is described. The circuit generally includes a phase imbalance detection circuit. The phase imbalance detection circuit may include a limiter. The phase imbalance detection circuit may be independent of gain imbalance. The circuit may also include a phase imbalance correction circuit. The phase imbalance detection circuit may control coupling between an inphase path and a quadrature path.

Abstract: A global navigation satellite system (GNSS) receiver includes at least one GNSS antenna configured to receive input signaling from at least a first GNSS source and a second GNSS source; an in-phase/quadrature (I/Q) mixer coupled to the at least one GNSS antenna and configured to process the input signaling to obtain complex intermediate signaling; a first complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a first frequency range to obtain first real output signaling; a second complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a second frequency range to obtain second real output signaling; and a signal combiner coupled to the first and second complex filters and configured to generate combined real output signaling by combining the first real output signaling and the second real output signaling.

Abstract: A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating a two-tone signal for performing linearity calibration of a radio frequency (RF) circuit. One example apparatus generally includes a tone generating circuit configured to generate a first single-tone signal from a digital clock signal and a mixer connected with the tone generating circuit and configured to mix the first single-tone signal with a second single-tone signal to provide a two-tone signal having frequencies at a sum and a difference of frequencies of the first and second single-tone signals.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating a two-tone signal for performing linearity calibration of a radio frequency (RF) circuit. One example apparatus generally includes a tone generating circuit configured to generate a first single-tone signal from a digital clock signal and a mixer connected with the tone generating circuit and configured to mix the first single-tone signal with a second single-tone signal to provide a two-tone signal having frequencies at a sum and a difference of frequencies of the first and second single-tone signals.

Abstract: A circuit for performing a residual side band calibration is described. The circuit generally includes a phase imbalance detection circuit. The phase imbalance detection circuit may include a limiter. The phase imbalance detection circuit may be independent of gain imbalance. The circuit may also include a phase imbalance correction circuit. The phase imbalance detection circuit may control coupling between an inphase path and a quadrature path.

Abstract: An apparatus includes a first bias circuit configured to generate a first current that varies with temperature according to a first slope. The apparatus also includes a second bias circuit configured to generate a second current that varies with temperature according to a second slope. The apparatus further includes a low noise amplifier including a transconductance stage that is responsive to an output of the first bias circuit. The apparatus also includes a load coupled to an output of the low noise amplifier and responsive to an output of the second bias circuit.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for performing quadrature combining and adjusting. One example circuit may include first through fourth mixing circuits. The first mixing circuit may multiply a radio frequency signal with a first local oscillating signal to generate a first frequency converted signal. The second mixing circuit may multiply a radio frequency (RF) signal with a second local oscillating signal, which may be about 90° out of phase with the first local oscillating signal, to generate a second frequency converted signal. The third and fourth mixing circuits may multiply the RF signal with the second and first signals, respectively, to generate third and fourth frequency converted signals, respectively. A first combining circuit may combine the first and third frequency converted signals, and a second combining circuit may combine the second and fourth frequency converted signals.

Abstract: A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

Abstract: Methods and circuits can down convert at least a first RF signal on a first path in a first frequency band to provide a first IF signal. A second RF signal on second path in a second frequency band can be down converted to provide a second IF signal. The first IF signal and the second IF signal are interspersed in the frequency domain, and the first frequency band is different from the second frequency band. A combiner can combine at least part of the first IF signal and the second IF signal to provide a combined signal on an output signal path for reception by a digital processing circuit. The first IF signal or second IF signal can be a Zero IF (ZIF), very low IF (VLIF), or Low IF (LIF) signal.