Patents by Inventor Cheng Hu

Cheng Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250206737
    Abstract: The present invention provides an improved process for the preparation of tucatinib, tucatinib intermediates, and the crystalline forms thereof. Specifically, the presently disclosed one-pot reaction processes save time and resources. The present invention improves the efficacy of producing Tucatinib, which can be performed under green chemistry.
    Type: Application
    Filed: December 20, 2024
    Publication date: June 26, 2025
    Inventors: Kuan-Hsun HUANG, Jing-Kai HUANG, Wen-Li SHIH, Jiunn-Cheh GUO, Tsung-Cheng HU
  • Publication number: 20250203940
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, a source/drain region disposed adjacent to the semiconductor layer, a gate structure disposed on the semiconductor layer, an interfacial spacer layer having a triangular cross-sectional profile disposed along sidewall of the gate structure, and a gate spacer. The gate spacer includes a first spacer portion having a first bottom surface with a substantially linear profile disposed on the semiconductor layer and a second spacer portion having a second bottom surface with a sloped profile disposed on the interfacial spacer layer.
    Type: Application
    Filed: June 12, 2024
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Hua HSU, Chia-I Lin, Kai-Min CHIEN, Yuan-Cheng HU, Yu-Jiun PENG, Kuo-Chin LIU, Ryan Chia-Jen CHEN
  • Patent number: 12334476
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
  • Patent number: 12334363
    Abstract: A purge controlling system includes a purge module and a control module. The purge module is arranged in the load port and is electrically connected with the control module. The purge module includes an air curtain unit, a flow control unit and a sensing unit. The control module controls the purge module to provide adequate gas flow of purge gas into the air curtain unit and form a gas curtain according to the displacement value of the door assembly.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: June 17, 2025
    Assignee: BRILLIAN NETWORK & AUTOMATION INTEGRATED SYSTEM CO., LTD.
    Inventors: Chen-Wei Ku, Han-Cheng Hu, Min-Che Li
  • Patent number: 12313598
    Abstract: A method of monitoring both liner wear and charge impact in an industrial mill uses a sensor mounted on an elongated element deployed through a shell into a liner of the mill. The elongated element wears at a same rate as the liner under conditions within the shell. Liner wear is related to a reduction in length of the elongated element as measured by travel time of an ultrasound wave, while location and strength of charge impact is related to change in amplitude of vibrations caused by the charge impact. Liner wear measurement can be improved by using shear ultrasound waves instead of conventional longitudinal ultrasound waves. A mill monitoring apparatus has a means for acquiring ultrasonic waves and audible sound waves using the same digitizer; a means for determining the angular position of the monitoring apparatus; and a means for supplying electric power to the apparatus.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 27, 2025
    Inventors: Zhigang Sun, Kuo-Ting Wu, Cheng Hu, Silvio Elton Krüger
  • Publication number: 20250167652
    Abstract: Provided is a low-torque ripple synchronous reluctance motor, including: a stator, including a plurality of stator slots and a plurality of stator teeth, each of the stator teeth including a stator tooth center; and a rotor, including a plurality of motor poles, each of the motor poles including a plurality of rotor barriers, the rotor barriers including a first rotor barrier to an n-th rotor barrier; a first rotor barrier end center line and a corresponding stator tooth center line defining a first included angle (?b), an n-th rotor barrier end center line and a corresponding stator tooth center line defines an included angle (?n), (?n)=[(n?1)×k+1]×?b, the real number (k) is any value within the range of 2±0.5, and the formula of the first included angle (?b) is any value within the range of the first included angle (?b)=36/Ns±0.5°, Ns is the number of stator slots.
    Type: Application
    Filed: August 20, 2024
    Publication date: May 22, 2025
    Inventors: Cheng-Hu CHEN, Jun-Wei XU
  • Publication number: 20250145592
    Abstract: The present disclosure relates generally to small molecule modulators of NLR Family Pyrin Domain Containing 3 (NL-RP3), or a pharmaceutically acceptable salt, isotopically enriched analog, stereoisomer, mixture of stereoisomers, or prodrug thereof, methods of making and intermediates thereof, and methods of using thereof. Further disclosed a method for treating a disease or condition mediated, at least in part, by NLRP3, the method comprising administering an effective amount of the pharmaceutical composition, to a subject in need thereof.
    Type: Application
    Filed: February 15, 2023
    Publication date: May 8, 2025
    Inventors: Alex L. Bagdasarian, Robert A. Craig, II, Javier de Vicente Fidalgo, Anthony A. Estrada, Brian M. Fox, Cheng Hu, Benjamin J. Huffman, Katrina W. Lexa, Lizanne G. Nilewski, Maksim Osipov, Arun Thottumkara
  • Patent number: 12266975
    Abstract: A motor rotor includes a rotor core and a plurality of reluctance parts. The rotor core includes a plurality of metal parts and an inner hole for the motor rotor, the inner hole of the motor rotor passes through the rotor core, and the areas of the metal parts form a rotor metal total area ?Ametal. The plurality of reluctance parts are disposed surrounding the inner hole of the motor rotor, each of the reluctance parts comprising a plurality of flux barriers penetrating through the rotor core. The areas of the flux barriers in all the reluctance parts form a flux barrier total area ?Aair. The sum of ?Aair and ?Ametal is a rotor effective total area, and the ratio of ?Aair to the rotor effective total area is a flux barrier ratio KA, which is expressed as K A = ? A air ? A air + ? A metal , and satisfies 0.25?KA?0.5.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: April 1, 2025
    Assignee: National Ilan University
    Inventors: Cheng-Hu Chen, Yu-Cheng Yao, Ruey-Yue Lin
  • Publication number: 20250060710
    Abstract: The present invention provides an AC power supply capable of programming output impedance and a method for simulating output impedance. The method comprises the following steps. The simulating command, selectively provided by a control circuit, is associated with a voltage adjustment value and a phase adjustment value of a test circuit. The control circuit calculates the voltage adjustment value and a preset voltage value to form a voltage command, and calculates the phase adjustment value and a preset phase value to form a phase command. A power supply circuit generates a simulated output voltage according to the voltage command and the phase command. The preset voltage value and the preset phase value are related to a preset output voltage provided by the power supply circuit, and the simulated output voltage is a simulation of the preset output voltage, provided by the power supply circuit, passed through the test circuit.
    Type: Application
    Filed: August 6, 2024
    Publication date: February 20, 2025
    Inventors: Ling-Wei KUNG, Guei-Cheng HU
  • Publication number: 20250055383
    Abstract: The present invention provides a two-way AC power conversion device configured to input or output a first AC power. The two-way AC power conversion device comprises a digital control module and a power conversion module. The digital control module generates a control signal. The power conversion module sets the first AC power to be input or output according to the control signal. Wherein when the digital control module determines a real-time voltage signal of the first AC power is abnormal, the power conversion module switches to provide a ground voltage according to the control signal.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Inventors: Yu HSU, Guei-Cheng HU
  • Publication number: 20250056684
    Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent resistor. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates a resistance of the resonant tank equivalent resistor according to the inductance of the resonant tank equivalent inductor, a time change value, a reference voltage value, a negative peak voltage value and a second expression.
    Type: Application
    Filed: December 27, 2023
    Publication date: February 13, 2025
    Inventors: Ming-Shi Huang, Zheng-Feng Li, Jhih-Cheng Hu, Yi-Min Chen, Chun-Wei Lin
  • Publication number: 20250011338
    Abstract: The present disclosure relates generally to compounds and compositions, intermediates, processes for their preparation, and their use as kinase inhibitors.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: Denali Therapeutics Inc.
    Inventors: Javier de Vicente Fidalgo, Anthony A. Estrada, Jianwen A. Feng, Brian Fox, Cinzia Maria Francini, Christopher R.H. Hale, Cheng Hu, Colin Philip Leslie, Maksim Osipov, Elena Serra, Zachary K. Sweeney, Arun Thottumkara
  • Publication number: 20250010597
    Abstract: A composite textile can include various layers, such as a nonwoven layer and a waterproof, breathable membrane. The composite textile can include various properties, such as waterproofness, water repellency, and the like. In addition, the composite textile can be manufactured using various techniques, which can be configured to impart desired properties. The composite textile can be suitable to form articles designed for inclement weather.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 9, 2025
    Inventors: Cheng Hu, Yang-Hua Ou, Christopher J. Ranalli, Lai-Hung Wan
  • Patent number: 12180211
    Abstract: The present disclosure relates generally to methods and compositions for preventing or arresting cell death and/or inflammation.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 31, 2024
    Assignee: DENALI THERAPEUTICS INC.
    Inventors: Anthony A. Estrada, Jianwen A. Feng, Brian Fox, Cheng Hu, Maksim Osipov, Zachary K. Sweeney, Javier de Vicente Fidalgo, Arun Thottumkara
  • Publication number: 20240404459
    Abstract: Provided are a display panel and a display device. The display panel includes first shift registers. A first shift register includes a node control module, a first control module, a first output module and a second output module. The node control module is configured to control a potential of the first node and a potential of the second node. The first control module is connected between the first node and a third node. The first output module is connected between a first power supply terminal and an output signal terminal. The second output module is connected between a second power supply terminal and the output signal terminal. In a first output stage, the first output module is turned on, the second output module is turned off and the first control module is turned off.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Applicant: Xiamen Tianma Display Technology Co., Ltd.
    Inventors: Zhoulin KE, Cheng HU
  • Publication number: 20240395218
    Abstract: Provided are a display panel and a display device which belong to the field of display technology. The display panel includes a driver circuit including a shift register, where the shift register includes an input circuit connected to at least an input signal terminal, a first clock signal line, and a first node; a control circuit connected to at least a first voltage signal line, a second voltage signal line, the first node, a second node, and a third node, where the first node and the third node are directly connected or connected through a first adjustment circuit; and an output circuit including a first output circuit and a second output circuit, where the first output circuit is connected to at least the first voltage signal line, the third node, and an output signal terminal.
    Type: Application
    Filed: August 6, 2024
    Publication date: November 28, 2024
    Applicant: Xiamen Tianma Display Technology Co., Ltd.
    Inventors: Cheng HU, Qingjun LAI
  • Publication number: 20240395195
    Abstract: A shift register circuit includes a first control module for controlling the potential of a first node in response to an input signal and a clock signal; a first output module for controlling the transmission path of a first level signal to a signal output terminal in response to the potential of the first node; a second control module for controlling a second level signal to be transmitted to a second node when the first level signal is transmitted to the signal output terminal and control the first level signal to be transmitted to the second node when the first level signal stops being transmitted to the signal output terminal; and a second output module for controlling the transmission path of the second level signal to the signal output terminal in response to the potential of the second node.
    Type: Application
    Filed: August 6, 2024
    Publication date: November 28, 2024
    Applicant: Xiamen Tianma Display Technology Co., Ltd.
    Inventors: Zhoulin KE, Cheng HU
  • Patent number: 12129263
    Abstract: The present disclosure relates generally to compounds and compositions, intermediates, processes for their preparation, and their use as kinase inhibitors.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 29, 2024
    Assignee: DENALI THERAPEUTICS INC.
    Inventors: Javier de Vicente Fidalgo, Anthony A. Estrada, Jianwen A. Feng, Brian Fox, Cinzia Maria Francini, Christopher R. H. Hale, Cheng Hu, Colin Philip Leslie, Maksim Osipov, Elena Serra, Zachary K. Sweeney, Arun Thottumkara
  • Patent number: 11996772
    Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Chroma ATE Inc.
    Inventors: Szu-Chieh Su, Wei-Chin Tseng, Chih-Hsien Wang, His-Ping Tsai, Wen-Chih Chen, Guei-Cheng Hu
  • Publication number: 20240113080
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu