Patents by Inventor Cheng Lee

Cheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240361884
    Abstract: The present disclosure generally relates to displaying widgets, managing widgets, and navigating user interfaces.
    Type: Application
    Filed: September 26, 2023
    Publication date: October 31, 2024
    Inventors: Edward CHAO, Taylor G. CARRIGAN, Jules K. FENNIS, Christopher P. FOSS, I-Cheng A. LEE, Jennifer D. PATTON
  • Publication number: 20240361852
    Abstract: A stylus pen including a pen unit, a switch, and a control unit is provided. The pen unit includes a tip, and a shaft connected to the tip. The control unit is switchable between a default mode and an alternative mode in response to operation on the switch. In the default mode, the control unit emits a default-mode wave of a default-mode frequency to the shaft. In the alternative mode, the control unit emits an alternative-mode wave to the shaft in a pulsating pattern. The pulsating pattern has a wave period that includes a working period where the control unit emits the alternative-mode wave of the default-mode frequency, and a non-working period where the control unit stops emitting the alternative-mode wave.
    Type: Application
    Filed: July 31, 2023
    Publication date: October 31, 2024
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Chih-Cheng LEE, Wen-Hao Kuo, Jyun-Ying Jin
  • Patent number: 12132095
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20240355847
    Abstract: A CMOS image sensor includes a unit pixel array including a photodiode array, a color filter array, a micro-lens array, and a grid isolation structure laterally separating adjacent color filters. The grid isolation structure includes a first low-n grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid being narrower than the second low-n grid. The color filter array includes color filter matrixes, all color filter matrixes have the same arrangement pattern. Sizes of color filters in each color filter matrix vary depending on locations of the color filters in the color filter matrix. In an edge portion, a distance between a center of a color filter matrix and a center of a corresponding unit pixel matrix in plan view varies depending on a location of the unit pixel matrix in the CMOS image sensor.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Ming-Hsien YANG, Wei-Chih WENG, Chun-Wei CHIA, Chun-Hao CHOU, Tse Yu TU, Chien Nan TU, Chun-Liang LU, Kuo-Cheng LEE
  • Patent number: 12125608
    Abstract: The present invention provides a differential paired cable with compensation functions, including: a first wire; a second wire; a first insulating layer; a second insulating layer; a ground wire; and a shielding layer. By controlling at least one of a length difference between the first insulating layer and the second insulating layer exposed outside of the shielding layer to be greater than 0.1 mm, a diameter difference between the first wire and the second wire to be greater than 0.005 mm, and a length difference between a welding portion of the first wire and a welding portion of the second wire to be greater than 0.05 mm, a signal transmission rate of one of the first wire and the second wire is compensated, so as to reduce an intra pair skew of the differential paired cable.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: October 22, 2024
    Inventor: James Cheng Lee
  • Patent number: 12125864
    Abstract: A method of making an image sensor includes depositing a shield layer over a substrate, wherein the substrate comprises a first photodiode (PD) and a second PD. The method further includes etching the shield layer to define a first recess aligned with the first PD and a second recess aligned with the second PD. The method further includes depositing a flicker reduction layer in the first recess and in the second recess. The method further includes etching the flicker reduction layer to remove the flicker reduction layer from the first recess.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Han Chen, Chen-Chun Chen, Fu-Cheng Chang, Kuo-Cheng Lee
  • Patent number: 12113042
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Liang Lu, Wei-Lin Chen, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12113086
    Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 12113365
    Abstract: A wireless charger with magnetic locating function includes an insulating body, a circuit module, a plug module and a wireless charging module. A front of the insulating body is recessed inward to form an opening, and the opening is further recessed inward to form an accommodating space. The circuit module is mounted in the accommodating space. The plug module is connected with the circuit module. The wireless charging module is mounted to the insulating body. The wireless charging module includes a magnetic core equipped with a charging coil, a bracket and an outer board. The charging coil is connected to the circuit module. The bracket covers the charging coil. The bracket has a plurality of accommodating grooves, and each accommodating groove is equipped with one magnetic element. The outer board covers the bracket.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: October 8, 2024
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventor: James Cheng Lee
  • Publication number: 20240332115
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
  • Publication number: 20240332325
    Abstract: In some implementations, a pixel array may include a near infrared (NIR) cut filter layer for visible light pixel sensors of the pixel array. The NIR cut filter layer is included in the pixel array to absorb or reflect NIR light for the visible light pixel sensors to reduce the amount of NIR light absorbed by the visible light pixel sensors. This increases the accuracy of the color information provided by the visible light pixel sensors, which can be used to produce more accurate images. In some implementations, the visible light pixel sensors and/or NIR pixel sensors may include high absorption regions to adjust the orientation of the angle of refraction for the visible light pixel sensors and/or the NIR pixel sensors, which may increase the quantum efficiency of the visible light pixel sensors and/or the NIR pixel sensors.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Kuo-Cheng LEE, Cheng-Ming WU
  • Publication number: 20240332784
    Abstract: An electronic device includes a casing and an antenna assembly. The casing has a waterproof area and a peripheral area. The peripheral area is defined at the periphery of the waterproof area. The antenna assembly is disposed at the peripheral area. The antenna assembly includes a housing, a circuit board, an antenna and a cover. The housing has a receiving recess. The circuit board is disposed in the receiving recess. The antenna is disposed in the receiving recess and electrically connected to the circuit board. The cover is mounted on the housing and hermetically seals the receiving recess.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventor: Kun-Cheng LEE
  • Patent number: 12104856
    Abstract: Some embodiments of the invention include a thermal ground plane with a variable thickness vapor core. For example, a thermal ground plan may include a first casing and a second casing where the second casing and the first casing configured to enclose a working fluid. The thermal ground plane may also include an evaporator region disposed at least partially on at least one of the first casing and the second casing; a condenser region disposed at least partially on at least one of the first casing and the second casing; and a wicking layer disposed between the first casing and the second casing a vapor core defined at least partially by a gap between the first casing and the second casing. The thickness of the gap can vary across the first casing and the second casing.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 1, 2024
    Assignees: Kelvin Thermal Technologies, Inc., THE REGENTS OF THE UNIVERSITY OF COLORADO, A BODY CORPORATE
    Inventors: Ryan John Lewis, Ronggui Yang, Yung-Cheng Lee
  • Patent number: 12107121
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
  • Patent number: 12107104
    Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photo sensors.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Po-Han Chen, Kuo-Cheng Lee, Fu-Cheng Chang
  • Patent number: 12107157
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 12105949
    Abstract: A touchpad device is to be operated by using a stylus pen, and includes a touchpad and a controller that are connected to each other. The controller is connected to an electronic device that includes a display panel, and operates in a stylus-pen mode where a handwriting area is presented on the display panel. When it is determined that a distance between the stylus pen and the touchpad is less than a preset pen-hover distance but is non-zero, the controller operates in a hover-move sub-mode where the controller outputs a control signal to enable the electronic device to present, in the handwriting area, the cursor moving, without presenting a trace of the cursor.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: October 1, 2024
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventor: Chih-Cheng Lee
  • Publication number: 20240321481
    Abstract: A method for producing a cable by covering with polytetrafluoroethylene and extrusion molding with a perfluoroalkoxy compound, including: covering an outer surface of a conductor with an insulation layer; and extrusion molding a skin layer on an outer surface of the insulation layer to form a cable. The insulation layer and the skin layer are made of polytetrafluoroethylene and a perfluoroalkoxy compound, respectively. The perfluoroalkoxy compound and polytetrafluoroethylene both have high temperature resistance, good electronic signal transmitting performance, and non-bonding surface, etc., and the perfluoroalkoxy compound has a Shore hardness of 60 to 70D, which can impart the skin layer a certain hardness, and is suitable for being extrusion molded on the outer surface of the insulation layer made of polytetrafluoroethylene, so as to support the insulation layer and prevent the insulation layer from being deformed. Therefore, the perfluoroalkoxy compound is the most suitable material for the skin layer.
    Type: Application
    Filed: December 22, 2023
    Publication date: September 26, 2024
    Inventor: James Cheng Lee
  • Publication number: 20240323555
    Abstract: An image sensor device may include a pixel sensor array and a black level correction (BLC) region. The BLC region may include a sensing region in a substrate and a light-blocking layer above the sensing region. An anti-reflection array may be formed in the light-blocking layer. The anti-reflection array includes holes, trenches, and/or other structural features such that the light-blocking layer includes two or more areas in which the top surface of the light-blocking layer is at different heights in the image sensor device. The different heights of the top surface of the light-blocking layer reduce the likelihood of light being reflected off of the light-blocking layer and toward the pixel sensor array. The anti-reflection array may reduce the likelihood of occurrence of flares or hot spots in images generated by the image sensor device, which may increase the image quality of the images generated by the image sensor device.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Inventors: Kuo-Cheng LEE, Ping-Hao LIN, Yun-Wei CHENG, Bo-Ge HUANG
  • Patent number: 12090579
    Abstract: A SnAgCuSbBi-based Pb-free solder alloy is disclosed. The disclosed solder alloy is particularly suitable for, but not limited to, producing solder joints, in the form of solder preforms, solder balls, solder powder, or solder paste (a mixture of solder powder and flux), for harsh environment electronics.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: September 17, 2024
    Assignee: INDIUM CORPORATION
    Inventors: Weiping Liu, Ning-Cheng Lee