Patents by Inventor Cheng Liu

Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189596
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11189621
    Abstract: A semiconductor layout structure for a dynamic random access memory (DRAM) array comprises a plurality of active areas, an isolation structure and a plurality of word lines in a semiconductor substrate, where the isolation structure is situated among the plurality of active areas. Each of the plurality of active areas comprises a first segment extending in a first direction and a second segment extending in a second direction, one end of the first segment connected to an end of the second segment such that the active area presents a “V” shape. Two of the plurality of word lines intersect and traverse the first and second segments in each of the active areas respectively.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 30, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih Cheng Liu
  • Publication number: 20210364296
    Abstract: A positioning method includes determining a positioning coordinate (x101,y101,z101) of a positioning device in a scene coordinate system o-xyz based on one or a combination of (1) an estimated coordinate (x1,y1,z1) of the positioning device in the scene coordinate system o-xyz; and (2) positions of image objects of one or more reference illumination sources of a plurality of illumination sources in a scene image, fixed coordinate positions (x0, y0, z0) of the one or more reference illumination sources of the plurality of illumination sources in the scene coordinate system o-xyz, and an included angle ? between an x-axis of the scene coordinate system o-xyz and an x?-axis of a positioning device coordinate system o?-x?y?z?.
    Type: Application
    Filed: September 25, 2018
    Publication date: November 25, 2021
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Cheng Liu, Changlin Leng
  • Publication number: 20210366909
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Application
    Filed: March 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J.H. Wang
  • Publication number: 20210366956
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Publication number: 20210364834
    Abstract: An array substrate, a method of driving an array substrate, a method of fabricating and array substrate, and a display panel including an array substrate are provided. The array substrate includes a base substrate (5), a first electrode (1) and a second electrode (2) on the base substrate (5), a polymer-dispersed liquid crystal layer (3) between the first electrode (1) and the second electrode (2), and a reflective layer (4) on a side of the polymer-dispersed liquid crystal layer (3) opposite from the base substrate (5). The polymer-dispersed liquid crystal layer (3) is configured to switch between a transparent state and an opaque state in accordance with a voltage applied between the first electrode (1) and the second electrode (2).
    Type: Application
    Filed: June 27, 2018
    Publication date: November 25, 2021
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Kui Gong, Xianxue Duan, Tianzhen Liu, Cheng Chen
  • Patent number: 11183100
    Abstract: A timing controller circuit of an electronic paper display apparatus including an image processing circuit and a timing controller is provided. The image processing circuit receives an image signal and analyzes the image signal according to a signal component of the image signal, so as to determine a display mode of the electronic paper display apparatus. The image processing circuit selects a driving signal waveform according to the determined display mode. The timing controller is electrically connected to the image processing circuit. The timing controller outputs the selected driving signal waveform to drive an electronic paper display panel of the electronic paper display apparatus to display image frames.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 23, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Cheng Liu, Pei-Lin Tien, Chi-Mao Hung
  • Patent number: 11180431
    Abstract: A turbulent fluidized bed reactor, device and method for preparing para-xylene and co-producing light olefins from methanol and/or dimethyl ether and toluene, resolving or improving the competition problem between an MTO reaction and an alkylation reaction during the process of producing para-xylene and co-producing light olefins from methanol and/or dimethyl ether and toluene, and achieving a synergistic effect between the MTO reaction and the alkylation reaction. By controlling the mass transfer and reaction, competition between the MTO reaction and the alkylation reaction is coordinated and optimized to facilitate a synergistic effect of the two reactions, so that the conversion rate of toluene, the yield of para-xylene, and the selectivity of light olefins are increased. The turbulent fluidized bed reactor includes a first reactor feed distributor and a number of second reactor feed distributors and are arranged sequentially along the gas flow direction.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 23, 2021
    Assignee: DALIAN INSTITUTE OF CHEMICAL PHYSICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Mao Ye, Tao Zhang, Zhongmin Liu, Jinling Zhang, Hailong Tang, Jinming Jia, Changqing He, Xiangao Wang, Cheng Zhang, Hua Li, Yinfeng Zhao, Chenggong Li
  • Patent number: 11182624
    Abstract: A method and system for constructing a transverse topological relationship and a memory are provided. In the method, lane group data in a high-definition map is acquired; for each lane group, a shared boundary line group of two adjacent lanes is sequentially extracted, and the number of parallel boundary line elements is determined; if the number is 1, a transverse topological relationship between the two adjacent lanes is not generated, otherwise the number and types of boundary line units on the parallel boundary line elements are determined; and if the number of the boundary line units is 1, the transverse topological relationship between the two adjacent lanes is generated, otherwise segmentation processing is performed on the lane group along a lane direction, and the transverse topological relationship between two adjacent lanes in each of segments, which are obtained by the segmentation processing on the lane group, is sequentially generated.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 23, 2021
    Assignee: WUHHAN KOTEL BIG DATE CORPORATION
    Inventors: Cheng Zhang, Xiaoyan Liu, Fen Liu
  • Publication number: 20210355288
    Abstract: In order to solve problems of strength and volume of part, the invention provides an article reinforced by multi-dimensional fibers and a method for manufacturing the article. The article includes a core portion and a shell layer portion. The core portion is made of thermoplastic resin and the fibers in which a majority of and a minority of the fibers are respectively arranged in a major and a minor directions. The method includes: preparing a core portion made of thermoplastic resin and the fibers in which a majority of and a minority of the fibers are respectively arranged in a major and a minor directions, loading the core portion into a mold, and forming a shell layer portion in the mold to enclose the core portion. The article manufactured by the method of this invention can reduce the weight and increase the strength of the parts.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Liang-Chieh CHAN, Yung-Cheng LIU, Jung-Chin YANG
  • Publication number: 20210355477
    Abstract: The present disclosure discloses a mutant of a lycopene epsilon cyclase (Lcye) gene crucial in a wheat carotenoid synthesis pathway and use thereof. The present disclosure provides the following proteins: (1) a protein obtained by substituting serine at position 253 of an Lcye-D1 protein with phenylalanine; (2) a derived protein that is obtained by subjecting the protein in (1) to substitution and/or deletion and/or addition of one or more amino acid residues and has the same ability as the protein in (1); (3) a protein that has a homology of more than 99%, more than 95%, more than 90%, more than 85%, or more than 80% with the amino acid sequence defined in any one of (1) and (2) and has the same function as the amino acid sequence; and (4) a fusion protein obtained by attaching a tag to N-terminus and/or C-terminus of the protein in any one of (1) to (3).
    Type: Application
    Filed: March 8, 2021
    Publication date: November 18, 2021
    Inventors: Shengnan ZHAI, Jianjun LIU, Haosheng LI, Jianmin SONG, Aifeng LIU, Xinyou CAO, Dungong CHENG, Zhendong ZHAO, Cheng LIU, Jun GUO, Ran HAN, Yan ZI, Faji LI, Xiaolu WANG
  • Publication number: 20210357736
    Abstract: A deep neural network hardware accelerator comprises: an AXI-4 bus interface, an input cache area, an output cache area, a weighting cache area, a weighting index cache area, an encoding module, a configurable state controller module, and a PE array. The input cache area and the output cache area are designed as a line cache structure; an encoder encodes weightings according to an ordered quantization set, the quantization set storing the possible value of the absolute value of all of the weightings after quantization. During the calculation of the accelerator, the PE unit reads data from the input cache area and the weighting index cache area to perform shift calculation, and sends the calculation result to the output cache area. The accelerator uses shift operations to replace floating point multiplication operations, reducing the requirements for computing resources, storage resources, and communication bandwidth, and increasing the calculation efficiency of the accelerator.
    Type: Application
    Filed: January 9, 2020
    Publication date: November 18, 2021
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Shengli LU, Wei PANG, Ruili WU, Yingbo FAN, Hao LIU, Cheng HUANG
  • Publication number: 20210353167
    Abstract: A method for determining one or more physiological parameters of a subject. The method includes providing a plurality of images of a vessel of the subject in response to illumination of the vessel to light of different wavelengths; converting each of the plurality of images of the vessel into at least two grayscale images, thereby generating a plurality of first grayscale images of a first wavelength range and a plurality of second grayscale images of a second wavelength range, the first wavelength range and the second wavelength range being different from each other; and determining the one or more physiological parameters of the subject based on at least the plurality of first grayscale images and the plurality of second grayscale images.
    Type: Application
    Filed: December 5, 2018
    Publication date: November 18, 2021
    Applicant: BOE Technology Group Co., Ltd.
    Inventor: Cheng Liu
  • Publication number: 20210359123
    Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Ya-Yu YANG, Shang-Ju TU, Tsung-Cheng CHANG, Chia-Cheng LIU
  • Publication number: 20210360086
    Abstract: Embodiments of this disclosure include an image obtaining method and apparatus, a server, and a storage medium. In the method, a target application process corresponding to a user identifier is obtained, by processing circuitry, from an application process set. A plurality of window image data that is currently generated is obtained, via a data obtaining module, when an image rendering function in the target application process is called. Image synthesis processing is performed on the plurality of window image data, to obtain a user interface image to be displayed. Further, a notification message that includes the user interface image is transmitted to a user terminal corresponding to the user identifier for display on a user interface.
    Type: Application
    Filed: July 27, 2021
    Publication date: November 18, 2021
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Gengxing HUANG, Wei YANG, Xue WEI, Cilang WANG, Borui YU, Zhiwei LIU, Guangdong YANG, Cheng ZENG
  • Publication number: 20210353626
    Abstract: Provided herein are modulators of beta-adrenergic receptors.
    Type: Application
    Filed: April 19, 2019
    Publication date: November 18, 2021
    Inventors: Roger K. SUNAHARA, Mary J. CLARK, Brian K. KOBILKA, Cheng ZHANG, Xiangyu LIU, Peter GMEINER, Anne STÖSSEL, Harald HÜBNER, Daniela DENGLER, Markus STANEK, Brian S. SHOICHET, Magdalena KORCZYNSKA, Jacob P. MAHONEY, Jonas KAINDL
  • Patent number: 11177307
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Patent number: 11175742
    Abstract: Disclosed embodiments provide techniques for intelligent media sharing with visualized positioning layout in real time. A floor plan is retrieved corresponding to the physical location of a sender electronic device. A zone boundary corresponding to the physical location of the sender electronic device is determined. A list of potential recipient electronic devices within the zone boundary is generated. A floor plan view is rendered on the sender electronic device. A graphical representation of the potential recipient electronic devices on the floor plan view is rendered, overlaid in a semi-transparent manner with a media selection interface on the sender electronic device. A selection is received for one or more media items using the media selection interface. A send request is received for one or more potential recipients, resulting in sending the one or more media items to at least one potential recipient in response to receiving a user interface request action.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Si Bin Fan, Su Liu, Yuan Yuan Wang, Cheng Xu
  • Patent number: 11177329
    Abstract: Display structures for controlling viewing angle color shift are described. In various embodiments, polarization sensitive diffusers, independent controlled cathode thicknesses, filtermasks, touch detection layers, and color filters are described.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Aleksandr N. Polyakov, Meng-Huan Ho, Yi Huang, Yi Qiao, David S. Hum, Jean-Pierre S. Guillou, Yanming Li, Jun Qi, KiBeom Kim, Kwang Ohk Cheon, Cheng Chen, Rui Liu, ByoungSuk Kim, Ying-Chih Wang, Hung Sheng Lin, Donghee Nam, Tyler R. Kakuda, Takahide Ishii, Yurii Morozov
  • Patent number: 11177343
    Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Cheng Gan, Wei Liu, Liang Chen