Patents by Inventor Cheng Liu

Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12044966
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Patent number: 12045600
    Abstract: The present disclosure provides a method for upgrading an Internet of Things (IoT) terminal device and an electronic device thereof. The method includes: determining a surveillance device and performing two-way verification with the surveillance device; sending, in response to successful two-way verification, a first upgrade instruction to at least one of the surveillance device and the terminal device, wherein a server communicates with the terminal device via the surveillance device, and the first upgrade instruction includes an encrypted upgrade file, encrypted server identification information, and an encrypted first check value.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: July 23, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Cheng Liu, Hongtao Guan
  • Publication number: 20240243165
    Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Chee-Wee LIU
  • Publication number: 20240242729
    Abstract: A processing circuit performing a speech enhancement method processes a to-be-processed signal to generate a target signal and executes a plurality of program codes or program instructions to perform the following steps: performing Fourier transform on the to-be-processed signal to generate a spectral signal of the to-be-processed signal; performing a first noise reduction processing on the spectral signal to obtain a first intermediate signal; performing a noise analysis on the first intermediate signal to obtain a noise feature; performing a second noise reduction processing on the first intermediate signal to generate a second intermediate signal when the noise feature does not satisfy a target condition; and performing inverse Fourier transform on the second intermediate signal to generate the target signal. The first noise reduction processing is different from the second noise reduction processing.
    Type: Application
    Filed: September 18, 2023
    Publication date: July 18, 2024
    Inventors: Jie Liu, Fei-Yang Tong, Cheng-Wei Zheng
  • Publication number: 20240243268
    Abstract: The present invention provides a metal and metallic ion mixed battery, which contains a positive electrode, a negative electrode, and an electrolyte, the positive electrode contains a positive electrode material with a metallic component of the battery; It only coats a small amount of negative electrode active materials that can form a metallic ion battery on the negative electrode and makes the negative electrode of the battery included dual advantages of metal and metallic ion battery; when charging, the metallic ions from the positive electrode are embedded in the negative electrode active material to make the battery have the characteristics of a metallic ion battery, and then continue to deposit on the current collector to form a metal battery. After several cycles, the battery can be charged and discharged stably and retains more than 99% of Coulombic efficiency, enhancing the overall energy density of the battery.
    Type: Application
    Filed: April 18, 2023
    Publication date: July 18, 2024
    Inventors: Bing-Joe Hwang, Sheng-Chiang Yang, Shi-Kai Jiang, Cheng-Cheng Liu, Ching-Ying Chen, Wei-Nien Su
  • Patent number: 12040370
    Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Cheng Hung, Yu-Jen Liu
  • Patent number: 12040948
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for grouping objects in a data management system. The method includes: detecting operation parameters of at least two of a plurality of objects in a data management system, and determining a rate of correlation between the at least two objects based on the detected operation parameters, wherein the rate of correlation indicates a degree of correlation between the at least two objects. The method further includes: comparing the determined rate of correlation with a predetermined threshold, and determining, based on the comparison of the determined rate of correlation with the predetermined threshold, grouping of the at least two objects. With this method, objects with a high degree of correlation are logically grouped together, so that a user can manage objects in batches in an efficient manner during object management, thus improving the system performance.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: July 16, 2024
    Assignee: DELL PRODUCTS L.P.
    Inventors: Weiyang Liu, Qi Wang, Ren Wang, Cheng Yang, Yuanyi Liu
  • Patent number: 12040353
    Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen
  • Patent number: 12040336
    Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Publication number: 20240234129
    Abstract: Methods and systems for forming structure comprising a threshold voltage tuning layer are disclosed. Exemplary methods include providing a treatment reactant to a reaction chamber to form a treated surface on the substrate surface and depositing threshold voltage tuning material overlying the treated surface. Additionally or alternatively, exemplary methods can include direct formation of metal silicide layers. Additionally or alternatively, exemplary methods can include use of an etchant.
    Type: Application
    Filed: January 3, 2024
    Publication date: July 11, 2024
    Inventors: Charles Dezelah, Michael Eugene Givens, Eric Jen Cheng Liu, Eric James Shero, Fu Tang, Marko Tuominen, Eva Elisabeth Tois, Andrea Illiberi, Tatiana Ivanova, Paul Ma, Gejian Zhao
  • Publication number: 20240229233
    Abstract: A method can comprise providing a zinc precursor to a reaction chamber comprising a substrate disposed therein; providing an oxygen species to the reaction chamber; forming a zinc oxide layer on the substrate in response to providing the zinc precursor and providing the oxygen species; and/or mitigating agglomeration of the zinc oxide layer. Mitigating agglomeration of the zinc oxide layer can comprise forming a capping layer on an outer surface of the zinc oxide layer such that the outer surface of the zinc oxide layer is not exposed to ambient oxygen, doping the zinc oxide layer with another material, and/or applying a post-deposition treatment to the zinc oxide layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 11, 2024
    Inventors: Fu Tang, Eric Jen Cheng Liu, Eric James Shero
  • Patent number: 12033919
    Abstract: Some embodiments relate to a semiconductor structure including a semiconductor substrate, and n interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a dielectric structure and a plurality of metal lines that are stacked over one another in the dielectric structure. A through substrate via (TSV) extends through the semiconductor substrate to contact a metal line of the plurality of metal lines. A protective sleeve is disposed along outer sidewalls of the TSV and separates the outer sidewalls of the TSV from the dielectric structure of the interconnect structure.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Xun Li, Min-Feng Kao, Hsing-Chih Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 12030821
    Abstract: A concrete interface agent relates to the technical field of concrete surface protection, an ingredient of the concrete interface agent comprises 55 to 100 parts by weight of a nano-calcium salt solution and a nano-SiO2 precursor, 0.1 to 0.4 parts by weight of a surfactant, 30 to 60 parts by weight of a silane coupling agent and 10 to 40 parts by weight of a polydimethylsilane, an ingredient of the nano-calcium salt solution comprises 2 to 5 parts by weight of a calcium hydroxide, 2 to 5 parts by weight of an acid catalyst and 200 to 500 parts by weight of an alcohol-based organic solvent, which can form a coating layer with higher hydrophobic angle on the concrete surface, reduce the water absorption of the concrete, and is not easy to crack after drying, which has more protective effect and longer service life than the existing TEOS interface agent.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: July 9, 2024
    Assignee: Qingdao University of Technology
    Inventors: Bo Pang, Zuquan Jin, Guoqing Geng, Yunsheng Zhang, Cheng Liu, Yidong Chen, Dafu Wang, Rusheng Qian
  • Patent number: 12032165
    Abstract: A glasses type display device including a front end assembly and a pair of legs is provided. Each of the pair of legs includes a front segment, a rear segment, a torsion mechanism, and a rotation mechanism. The torsion mechanism is disposed between the front end assembly and the front segment. The rotation mechanism is disposed between the front segment and the rear segment.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: July 9, 2024
    Assignee: HTC Corporation
    Inventors: Tung-Hsin Yeh, Ching-Ho Li, Wei-Cheng Liu, Chun-Lung Chu
  • Patent number: 12034037
    Abstract: Some embodiments relate to a method. In the method, semiconductor devices are formed on a frontside of a semiconductor substrate. A trench is formed in a backside of the semiconductor substrate. Conductive and insulating layers are alternatingly formed in the trench on the backside of the semiconductor substrate to establish a backside capacitor. A backside interconnect structure is formed on the backside of the semiconductor substrate to couple to capacitor electrodes of the backside capacitor.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu
  • Publication number: 20240222261
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first die and a second die. The first die includes a substrate, an interconnection structure and a capacitor structure. The substrate has a front-side surface and a back-side surface. The interconnection structure is disposed over the front-side surface. The capacitor structure extends from the back-side surface to the front-side surface and into the interconnection structure. The second die is disposed over the back-side surface and is bonded to the first die. A method for forming a semiconductor structure is also provided.
    Type: Application
    Filed: January 4, 2023
    Publication date: July 4, 2024
    Inventors: MIN-FENG KAO, DUN-NIAN YAUNG, HSING-CHIH LIN, JEN-CHENG LIU
  • Publication number: 20240217470
    Abstract: The present invention relates to a steering wheel component (2) and a steering wheel assembly comprising the steering wheel component (2). The steering wheel component (2) comprises an airbag door cover (21), wherein the airbag door cover (21) has an integral panel (210), wherein the panel (210) has a first area (31) for closing an airbag housing (22) and a second area (32), which is arranged beside the first area (31) and is configured as an operating surface for a multifunction switch (3).
    Type: Application
    Filed: July 28, 2022
    Publication date: July 4, 2024
    Applicant: Yanfeng International Automotive Technology Co., Ltd.
    Inventors: Cheng LIU, Zhiyuan CHEN, Lei YANG, Kuan LIU
  • Publication number: 20240222407
    Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
    Type: Application
    Filed: February 15, 2024
    Publication date: July 4, 2024
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Publication number: 20240223161
    Abstract: Pseudo resistor having an auto-tune function automatically calibrates resistance of the pseudo resistor and compensates for DC drift based on an output signal of an electrical circuit to which the pseudo resistor is coupled, as to mitigate signal phenomenon in the output signal caused by PVT variation. The pseudo resistor includes first transistor, second transistor, and adder. The first terminal of the second transistor is coupled to the first terminal of the first transistor and forms a first common node. The control terminal of the first transistor is coupled to the control terminal of the second transistor and forms second common node. The adder is coupled between the first and second common nodes and configured to receive adjustment voltage for generating a bias voltage for controlling the first and second transistors, where the adjustment voltage corresponds to the output signal coupled to the second terminal of the second transistor.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chih-Yuan Chang, Yu-Te Liao, Wei Cheng Liu
  • Publication number: 20240218962
    Abstract: A device for mounting an electronic display to a wall includes: a fixing plate defining an inner gear wheel; a display-mounting bracket configured to vertically tilt relative to the fixing plate, the display-mounting bracket having a proximal extension with an eccentric gear having a locking shaft, the eccentric gear being configured to engage with the inner gear wheel; a spring coupled between the main fixing plate and the locking shaft such that the spring retains a vertical-tilt orientation of the display-mounting bracket relative to the main fixing plate; and an adjustment screw coupled to the lower end of the tension spring, wherein rotation of the adjustment screw expands or compresses the spring.
    Type: Application
    Filed: May 30, 2023
    Publication date: July 4, 2024
    Applicant: Shenzhen Bestqi Innovation Technology Co., Ltd.
    Inventors: Cheng LIU, Yuan HUO