Abstract: A computer-implemented method is provided for model training performed by a processing system. The method comprises determining a set of first weights based on a first matrix associated with a source model, determining a set of second weights based on the set of first weights, forming a second matrix associated with a target model based on the set of first weights and the set of second weights, initializing the target model based on the second matrix, and training the target model.

Abstract: A semiconductor structure includes at least one sub-word line driver. The sub-word line driver includes a plurality of first active areas and a main-word line. The main-word line includes a plurality of first gates and a plurality of second gates interconnected. The plurality of first gates correspond to the plurality of first active areas. An extension direction of the plurality of first gates in the main-word line and/or an extension direction of at least part of the second gates in the main-word line intersects both a first direction and a second direction. The first direction is parallel to a direction in which the first active areas extend, and the second direction is parallel to a plane in which the first active areas are located and is perpendicular to the first direction.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: A system for a sandy soil landfill solid waste polluted river channel, includes a ground water interception and diversion system and a river channel ecological remediation system. The ground water interception and diversion system includes a water intake well arranged upstream of ground water in a landfill area, a buffer pool communicated with the water intake well, and a wastewater treatment system communicated with the buffer pool. The water intake well, the buffer pool, and the wastewater treatment system are communicated through a wastewater pipe. An electric wastewater valve and a variable frequency water pump are arranged on the wastewater pipe in sequence. The river channel ecological remediation system includes an impermeable layer arranged at a bottom of a river channel and ecological bank protections arranged on both sides of a river channel slope.

Abstract: A method for protecting a power system having inverter-interfaced renewable energy sources is provided. The power system includes an inverter and a control system. The control system includes a current controller including a saturation limiter and a proportional and integral (PI) controller, a phase-locked system, and a low-voltage ride-through (LVRT)control unit. The method includes: by using a Park transformation matrix, determining an output voltage of the inverter; determining a modulated voltage of the output voltage; upon detecting a grid fault, obtaining current references by the LVRT control unit; determining a fault current in a first stage of a transient phase of the grid fault; determining a fault current in a second stage of the transient phase; determining a fault current in a third stage of the transient phase; and switching the control system to a fault control mode by tracking the fault currents in the first, second and third stages, to the current references.

Abstract: A substrate processing apparatus comprises a chamber member that defines an interior volume that has an aspect ratio. The chamber member comprises a pair of laterally opposing inlet walls and a loading port. Each of the pair of laterally opposing inlet walls has an inlet port configured to receive output from a remote plasma source. The loading port is arranged between the pair of inlet walls, configured to allow passage of a substrate into the interior volume.

Abstract: A heavy-duty, high-power and large-torque chassis dynamometer for a multi-environmental system, comprising a power testing platform disposed on the ground and a rack located below the power testing platform. A fixed base and a sliding base are sequentially disposed on an inner side of the rack in a length direction of the power testing platform, a pair of first hub assemblies are mounted on the fixed base through a plurality of support frames, a sliding platform is disposed on the sliding base, and a pair of second hub assemblies are mounted on the sliding platform through a plurality of support frames. Tension sensor assemblies are connected to outer circumferences of the first hub assemblies and outer circumferences of the second hub assemblies, and are fixedly disposed on the support frames.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A micro-metering device with a constant flow rate, including a rotary shear valve, a mounting seat, a rotation drive assembly, an injection drive assembly and a controller. The rotary shear valve includes a valve main body and a valve spool. The valve main body is provided with a main flow channel and a plurality of branch flow channels. The valve spool is rotatably arranged inside the valve main body, and is configured to communicate the main flow channel with different branch flow channels. A pressure sensor is provided inside the valve main body, and is communicated with the main flow channel. The pressure sensor is configured for detecting a pressure inside the main flow channel. Whether the switching of the liquid path is correct is determined according to the pressure in the main flow channel.

Abstract: The described positional awareness techniques employing sensory data gathering and analysis hardware with reference to specific example implementations implement improvements in the use of sensors, techniques and hardware design that can enable specific embodiments to find new area to cover by a robot encountering an unexpected obstacle traversing an area in which the robot is performing an area coverage task. The sensory data are gathered from an operational camera and one or more auxiliary sensors.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: A method of fabricating a device includes providing a plurality of fins extending from a substrate. In some embodiments, each fin of the plurality of fins includes a plurality of semiconductor channel layers. In various example, the method further includes performing an ion implantation process into a first fin of the plurality of fins to introduce a dopant species into a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin. In some embodiments, the ion implantation process deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin.

Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Abstract: This application relates to a negative electrode plate, a secondary battery and apparatus thereof. The secondary battery of the present application comprises a negative electrode plate, the negative electrode plate comprises a composite current collector and a negative electrode active material layer disposed on at least one surface of the composite current collector, the negative electrode active material layer comprises a silicon-based active material, the silicon-based active material accounts for 0.5 wt % to 50 wt % of total mass of the negative electrode active material layer, and the composite current collector comprises a polymer support layer and a metal conductive layer disposed on at least one surface of the polymer support layer. The secondary battery and the negative electrode plate achieve good coordination between the current collector and the negative electrode active material layer.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: The present disclosure provides a dog nose print recognition method and system. The dog nose print recognition method includes: collecting a nose image of a dog, acquiring the nose image, and processing the nose image to obtain a plurality of regional images to be recognized; performing key point detection on the plurality of regional images to be recognized to obtain key points corresponding to the regional images to be recognized, and using the key points to perform alignment processing of the regional images to be recognized to obtain aligned regional images to be recognized; and performing dog nose print feature vector extraction and recognition on the aligned regional images to be recognized, and determining a dog identity recognition result through the dog nose print feature vector extraction and recognition. The system includes modules corresponding to the steps of the method.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.