Abstract: Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: In some implementations, a pixel array may include a near infrared (NIR) cut filter layer for visible light pixel sensors of the pixel array. The NIR cut filter layer is included in the pixel array to absorb or reflect NIR light for the visible light pixel sensors to reduce the amount of MR light absorbed by the visible light pixel sensors. This increases the accuracy of the color information provided by the visible light pixel sensors, which can be used to produce more accurate images. In some implementations, the visible light pixel sensors and/or MR pixel sensors may include high absorption regions to adjust the orientation of the angle of refraction for the visible light pixel sensors and/or the MR pixel sensors, which may increase the quantum efficiency of the visible light pixel sensors and/or the MR pixel sensors.

Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Abstract: A pixel sensor may include a deep trench isolation (DTI) structure that extends the full height of a substrate in which a photodiode of the pixel sensor is included. Incident light entering the pixel sensor at a non-orthogonal angle is absorbed or reflected by the DTI structure along the full height of the substrate. In this way, the DTI structure may reduce, minimize, and/or prevent the incident light from traveling through the pixel sensor and into an adjacent pixel sensor along the full height of the substrate. This may increase the spatial resolution of an image sensor in which the DTI structure is included, may increase the overall sensitivity of the image sensor, may reduce and/or prevent color mixing between pixel sensors of the image sensor, and/or may decrease image noise after color correction.

Abstract: A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: A pixel sensor may include a vertically arranged (or vertically stacked) photodiode region and floating diffusion region. The vertical arrangement permits the photodiode region to occupy a larger area of a pixel sensor of a given size relative to a horizontal arrangement, which increases the area in which the photodiode region can collect photons. This increases performance of the pixel sensor and permits the overall size of the pixel sensor to be reduced. Moreover, the transfer gate may surround at least a portion of the floating diffusion region and the photodiode region, which provides a larger gate switching area relative to a horizontal arrangement. The increased gate switching area may provide greater control over the transfer of the photocurrent and/or may reduce switching delay for the pixel sensor.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.

Abstract: A pixel array includes octagon-shaped pixel sensors and square-shaped pixel sensors. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. Moreover, the pixel array may include a combination of red, green, and blue pixel sensors to obtain color information from incident light; yellow pixel sensors for blue and green color enhancement and correction for the pixel array; near infrared (NIR) pixel sensors to increase contour sharpness and low light performance for the pixel array; and/or white pixel sensors to increase light sensitivity and brightness for the pixel array. The capability to configure different sizes and types of pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.

Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.

Abstract: Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.

Abstract: Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate. The gate stack is formed over the first region. The method includes forming a negative photoresist layer over the first region and a first portion of the conductive layer over the isolation structure to cover the gate stack. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over a second portion of the conductive layer. The method includes removing the second portion through the trenches. The method includes removing the mask layer. The method includes removing the negative photoresist layer.