Abstract: A modified method for forming stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. First openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings, which are generally recessed due to overetching to completely remove the polysilicon on the insulating surface. A Si.sub.3 N.sub.4 etch-stop layer is deposited to protect the exposed sidewalls in the first openings. A disposable second SiO.sub.2 insulating layer is deposited and second openings are etched over and to the node contacts for forming bottom electrodes. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the etch-stop layer.

Abstract: A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed.

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact.

Abstract: A process for obtaining global planarization, or a smooth top surface topography, for an insulator layer overlying a semiconductor chip, with DRAM device structures, featuring crown shaped capacitor structures, and with peripheral, non-DRAM devices, has been developed. The process features the use of a thin silicon nitride shape, used as a hard mask, overlying insulator layers in the peripheral, non-DRAM device region, and used to prevent removal of these underlying insulator layers, during a wet etch procedure which is used to expose the vertical features of crown shaped, storage node structures, in the DRAM device region. The prevention of removal of insulator, located overlying the peripheral, non-DRAM device region, allows a subsequent, planarized, overlying insulator layer, to provide the desired smooth top surface topography for the entire semiconductor chip.

Abstract: A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.

Abstract: A method for making cylinder-shaped stacked capacitors for DRAMs is described. A planar first insulating layer is formed over device areas. An etch-stop layer, a second insulating layer, and a polish-back endpoint detect layer are deposited in which cylinder-shaped capacitors with node contacts are formed. First openings for node contacts are etched in the polish-back and second insulating layers to the etch-stop layer aligned over the device areas. Wider second openings, aligned over the first openings, are etched through the polish-back layer, and also removes the etch-stop layer in the first openings. The second insulating layer in the second openings is etched to the etch-stop layer, while the first insulating layer is etched in the first openings for node contact openings. A doped first polysilicon layer is deposited and polished back to the polish-back detect layer to form concurrently the node contacts in the first openings and bottom electrodes in the second openings.

Abstract: A method to eliminate voids in the dielectric oxide between closely spaced conducting lines is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A high density plasma (HDP) dielectric layer is deposited overlying the conductive lines and the substrate. The HDP layer is etched through to expose the edges of the conducting lines. An insulating layer is deposited overlying the HDP layer and conducting lines. A chemical mechanical polishing (CMP) is used to remove the peaks of the insulating layer, exposing the HDP layer in the area overlying the conducting lines. The exposed HDP layer is etched away exposing the top surface of the conducting lines. The insulating layer is then selectively etched away. Spacers may then be added along the sidewalls of the conductor. Finally, a second HDP layer is deposited overlying the first dielectric layer and conducting lines free from voids. The integrated circuit device is completed.

Abstract: A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick insulator layer. Removal of the regions of polysilicon, residing on the top surface of the thick insulator layer, results in a crown shaped, polysilicon storage node structure, in the opening, in the thick insulator layer. The crown shaped, polysilicon storage node structure, was protected from the polysilicon removal procedure, by a photoresist plug, formed overlying the polysilicon layer, in the opening, in the thick insulator layer. The photoresist plug was formed via photoresist application, exposure, and the development of exposed photoresist regions.

Abstract: A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer.

Abstract: A process for forming a crown shaped storage node structure, for a DRAM capacitor structure, has been developed. The process features the patterning of a top portion, of a storage node contact plug structure, after patterning of the crown shaped storage node structure, and after removal of a silicon oxide layer, used for the definition of the crown shaped storage node structure. The sequence of patterning steps allows mis-alignment between the crown shaped storage node structure, and the underlying storage node contact hole, to occur without vulnerability to insulator layers used to passivate the transfer gate transistors, of the DRAM cell. This process also features the use of a photoresist plug, used to protect a bottom shape, of the crown shaped storage node structure during the crown shaped storage node, and the storage node contact plug structure, patterning procedures.

Abstract: A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85.

Abstract: A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems.