Patents by Inventor Cheng Tsai

Cheng Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176211
    Abstract: An imaging lens assembly module includes an imaging lens assembly and a variable aperture module. The imaging lens assembly has an optical axis. The variable aperture module includes a light blocking sheet set, a fixed element, a movable element, and an annular light blocking portion. The light blocking sheet set includes at least two light blocking sheets, wherein the at least two light blocking sheets are mutually stacked along a circumferential direction surrounding the optical axis to form a variable aperture opening. The fixed element has a sidewall structure. The annular light blocking portion surrounds the optical axis to form a fixed aperture opening.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Heng-Yi SU, Chia-Cheng TSAI, Hao-Jan CHEN, Ming-Ta CHOU
  • Patent number: 11996058
    Abstract: A display device is provided and includes a display panel, a light source, a light source controller, and a timing controller. The light source is adjacent to the display panel. The light source controller is electrically connected to the light source. The timing controller is electrically connected to the light source controller and the display panel. The timing controller includes a decoding unit and first and second processing units. The first processing unit is electrically connected to the decoding unit and the display panel. The second processing unit is electrically connected to the decoding unit and the light source controller. The decoding unit provides a refresh signal to the first and second processing units so that the display panel refreshes displayed content in a first refresh sequence according to first refresh rates, and the light source refreshes brightness in a second refresh sequence according to second refresh rates.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 28, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Huang-Chi Chao, Wei-Cheng Tsai, Ming-Chi Weng, Yu-Hsin Feng, Cheng-Tso Hsiao, Ming-Feng Hsieh, Chien-Hung Chan
  • Patent number: 11992053
    Abstract: A vaporizer comprises an absorber, a heating element, and a porous cover layer. The absorber is configured to absorb a material to be vaporized. The heating element is configured to heat and vaporize the material to be vaporized in the absorber, and includes a first electrode portion, a second electrode portion, and an electrically conductive connecting member connected between the first electrode portion and the second electrode portion. The porous cover layer covers at least a portion of the heating element without covering the first and second electrode portions. A ratio of an area of the porous cover layer to an area of the electrically conductive connecting member is defined as a covering ratio, which is at least 50%. A porosity of the porous cover layer ranges from 30% to 75%.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 28, 2024
    Assignee: POLYTRONICS TECHNOLOGY CORP.
    Inventors: Po-Chih Shen, Tong Cheng Tsai, Yu Sian Jhou
  • Patent number: 11996772
    Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Chroma ATE Inc.
    Inventors: Szu-Chieh Su, Wei-Chin Tseng, Chih-Hsien Wang, His-Ping Tsai, Wen-Chih Chen, Guei-Cheng Hu
  • Publication number: 20240170355
    Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier structure, and an interposer is stacked on the electronic element. Further, a wire is connected to the interposer and grounds the carrier structure, such that the wire and the interposer surround the electronic element. Therefore, the wire can be used as a shielding element when the electronic package is in operation to prevent the electronic element from being subjected to external electromagnetic interference.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 23, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chien-Cheng LIN
  • Patent number: 11990558
    Abstract: A method for producing a transferable array of light emitting devices includes forming a plurality of light emitting devices on a temporary substrate, forming at least one supporting member that is directly connected to a release layer of at least one of the light emitting devices, connecting a supporting substrate only with the at least one supporting member so that the at least one supporting member extends from the release layer of the at least one of the light emitting devices to the supporting substrate and so that the light emitting devices are spaced apart from the supporting substrate, and removing the temporary substrate. The transferable array produced by the method is also disclosed.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 21, 2024
    Assignee: Xiamen San'an Optoelectronics Co., Ltd.
    Inventors: Cheng Meng, Chingyuan Tsai, Chun-I Wu
  • Patent number: 11990510
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Publication number: 20240162218
    Abstract: An electrostatic discharge device including a gate structure, a plurality of first doped regions, and a plurality of second doped regions. The gate structure is disposed on a substrate. The gate structure includes a body part and a plurality of extension parts. The extension parts are connected with the body part, and an extension direction of the body part is different from an extension direction of the extension parts. The first doped regions are located in the substrate between the extension parts. The second doped regions are located in the substrate at two outer sides of the extension parts. The first doped regions and the second doped regions have different conductivity types.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 16, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chih Hsiang Chang, Mei-Ling Chao, Yin-Chia Tsai, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20240162318
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
  • Publication number: 20240152671
    Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chi-Ming Lee, Chung-An Wang, Cheok Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai
  • Publication number: 20240142833
    Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Applicant: Innolux Corporation
    Inventors: Wei-Yen Chiu, Ming-Jou Tai, You-Cheng Lu, Yi-Shiuan Cherng, Yi-Hsiu Wu, Chia-Hao Tsai, Yung-Hsun Wu
  • Patent number: 11970894
    Abstract: A double-axis hinge structure including a fixing member, a first shaft, a first guiding portion, a second shaft, a second guiding portion, and a slide guiding member is provided. The first shaft and the second shaft pass through the fixing member and the slide guiding member. The first guiding portion and the second guiding portion are respectively integrally formed on the first shaft and the second shaft. The slide guiding member has a third guiding portion and a fourth guiding portion. When one or both of the first shaft and the second shaft rotates relative to the fixing member, the guidance between the first guiding portion and the third guiding portion and/or the second guiding portion and the fourth guiding portion drives the slide guiding member to slide, so that the first shaft and the second shaft synchronously rotate in opposite directions by the same amount of rotation.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 30, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Shiue Jan, Jyh-Chyang Tzou, Han-Tsai Liu
  • Patent number: 11972981
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung
  • Publication number: 20240136298
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20240134136
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Publication number: 20240133467
    Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 25, 2024
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Yu-Xiang GENG, Chun-Chieh CHEN, Ling-Cheng TSENG, Yi-Wen TSAI, Ching-Yao HUANG
  • Patent number: 11968843
    Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
  • Publication number: 20240126633
    Abstract: A method for responding to a command is adapted for a storage device. The method for responding to a command includes following steps of: sequentially receiving a first command and a second command by a bridge of the storage device from a host; executing the first command and the second command to generate a status completion signal or a status error signal by the bridge; and detecting an error state of at least one of the first command and the second command to execute a response mode or an idle mode by the bridge according to the error state so as to respond to the host.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 18, 2024
    Inventors: Yi Cheng TSAI, Sung-Kao LIU, Cheng-Yuan HSIAO, Po-Hao CHEN
  • Patent number: 11961913
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961900
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang