Patents by Inventor Cheng Wang

Cheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11965217
    Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
  • Publication number: 20240127860
    Abstract: Provided are an audio/video processing method and apparatus, a device, and a storage medium. The method comprises: displaying text data corresponding to an audio/video to be edited, wherein the text data has a mapping relation with an audio/video timestamp of said audio/video; displaying said audio/video according to a time axis track; in response to a preset operation triggered for target text data in the text data, determining an audio/video timestamp corresponding to the target text data as a target audio/video timestamp; and processing, on the basis of the preset operation, an audio/video clip corresponding to the target audio/video timestamp in said audio/video.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: Weiming ZHENG, Cheng LI, Xuelun FU, Yixiu HUANG, Rui XIA, Xin ZHENG, Lin BAO, Weisi WANG, Chen DING
  • Publication number: 20240128377
    Abstract: A display panel includes a gate electrode, a source electrode, a drain electrode, and a metal oxide layer disposed corresponding to the gate electrode. The metal oxide layer includes a lower metal oxide layer and an upper metal oxide layer stacked on the lower metal oxide layer. The lower metal oxide layer includes an indium oxide and a lanthanoid oxide. The upper metal oxide layer is located on a surface of the lower metal oxide layer adjacent to the source electrode and the drain electrode. The source electrode and the drain electrode are connected to the upper metal oxide layer. The upper metal oxide layer includes an indium oxide and a lanthanoid oxide, and the upper metal oxide layer includes polycrystalline phase.
    Type: Application
    Filed: December 30, 2022
    Publication date: April 18, 2024
    Applicant: GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jiahui Huang, Zhixiong Jiang, Qiang Wang, Cheng Gong, Mingjiue Yu, Zhihui Cai
  • Publication number: 20240128232
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Publication number: 20240128216
    Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240124307
    Abstract: The present disclosure provides a method for preparing lithium iron phosphate from ferric hydroxyphosphate, including: purifying ferrous sulfate to form a ferrous sulfate solution, adding hydrogen peroxide, phosphoric acid, an ammonium dihydrogen phosphate solution and ammonia water into the ferrous sulfate solution and then reacting to form a mixed slurry, holding the mixed slurry at a temperature for a period of time, and then washing with water and subjecting to press filtration to form ferric hydroxyphosphate precursors with different iron-phosphorus ratios; then flash drying, sintering at a high temperature, and pulverizing to obtain ferric hydroxyphosphate precursors with different iron-phosphorus ratios and different specific surface areas.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Jie Sun, Ji Yang, Yihua Wei, Zhonglin He, Jianhao He, Zhongzhu Xu, Jing Mei, Guangchun Cheng, Shuo Lin, Cheng Xu, Pingjun Lin, Menghua Yu, Bin Wang, Xiaoting Wang, Chao Liu, Yuan Yao
  • Patent number: 11962949
    Abstract: A method of performing air pollution estimation is provided. The method is to be implemented using a processor of a computer device and includes: generating a spectral image based on an original color image of an environment under test using a spectral transformation matrix; supplying the spectral image as an input into an estimating model for air pollution estimation; and obtaining an estimation result from the estimating model indicating a degree of air pollution of the environment under test.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 16, 2024
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Chia-Cheng Huang, Ting-Chun Men
  • Patent number: 11961915
    Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shi Ning Ju, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Wen-Ting Lan
  • Patent number: 11959970
    Abstract: One or more embodiments of the present specification provide a method and device for capacity degradation prediction of a lithium-ion battery. The method comprises the following steps: acquiring an original battery discharge capacity; decomposing the original battery discharge capacity through a predetermined mode decomposition method to obtain battery discharge capacities composed of a plurality of different frequency signals; inputting the respective frequency signals into a pre-constructed capacity prediction model to obtain capacity prediction results corresponding to the respective frequency signals; selecting capacity prediction result that satisfies a predetermined relevance condition corresponding to the respective frequency signals; and reconstructing the finally predicted battery discharge capacity according to the capacity prediction result that satisfies the predetermined relevance condition.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: April 16, 2024
    Assignee: Beijing Institute of Technology
    Inventors: Huixing Meng, Mengyao Geng, Cheng Wang, Jinduo Xing
  • Patent number: 11962150
    Abstract: A method for protecting a power system having inverter-interfaced renewable energy sources is provided. The power system includes an inverter and a control system. The control system includes a current controller including a saturation limiter and a proportional and integral (PI) controller, a phase-locked system, and a low-voltage ride-through (LVRT)control unit. The method includes: by using a Park transformation matrix, determining an output voltage of the inverter; determining a modulated voltage of the output voltage; upon detecting a grid fault, obtaining current references by the LVRT control unit; determining a fault current in a first stage of a transient phase of the grid fault; determining a fault current in a second stage of the transient phase; determining a fault current in a third stage of the transient phase; and switching the control system to a fault control mode by tracking the fault currents in the first, second and third stages, to the current references.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: April 16, 2024
    Assignee: NORTH CHINA ELECTRIC POWER UNIVERSITY
    Inventors: Tianshu Bi, Ke Jia, Qian Liu, Hao Liu, Cheng Wang
  • Patent number: 11961484
    Abstract: The application discloses a correction method, correction device and correction system for free full-screen splicing. According to the application, influence of reasons such as an external light source and a camera angle is eliminated based on curved surface simulation over color information data of multiple pixels, so that free full splicing may be implemented when a spliced display screen, after being used, is disassembled and transferred to another site for re-splicing.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 16, 2024
    Assignee: XI'AN NOVASTAR TECH CO., LTD.
    Inventors: Cheng Yang, Yonghong Ai, Yu Wang
  • Patent number: 11961900
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11961913
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961840
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961763
    Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11962296
    Abstract: Disclosed herein is a flexible sensing interface, comprising: a sensor, comprising: a core; an inner electrode in the form of a conductive material in contact with the core; an inner dielectric material substantially encasing the inner electrode; an outer electrode in the form of a conductive material in contact with the inner dielectric material and in electrical communication with the inner electrode; and an outer dielectric material substantially encasing the outer electrode; wherein the inner dielectric material and the outer dielectric material comprise an elastic material. Also disclosed herein are systems and methods for making and using the same.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 16, 2024
    Assignee: Georgia Tech Research Corporation
    Inventors: Seyedeh Fereshteh Shahmiri, Chaoyu Chen, Gregory D. Abowd, Shivan Mittal, Thad Eugene Starner, Yi-Cheng Wang, Zhong Lin Wang, Dingtian Zhang, Steven L. Zhang, Anandghan Waghmare
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Patent number: D1023802
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: TRON FUTURE TECH INC.
    Inventors: Yu-Jiu Wang, Chia-Cheng Kung, Yu-Ju Chen, Boon How Teoh