Patents by Inventor Cheng Wang

Cheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240237282
    Abstract: A liquid cooling system includes a cold plate thermally coupled to a heat-generating electronic component, a heat removal unit fluidly coupled to the cold plate, and a valve fluidly coupled to the cold plate and the heat removal unit. The cold plate has an internal fluid pathway. The heat removal unit delivers the cooling fluid to the cold plate, receives heated cooling fluid from the cold plate, and removes heat from the heated cooling fluid. When the valve is in a first orientation, the cold plate and the heat removal unit are fluidly coupled in a first configuration and the cooling fluid flows through the internal fluid pathway in a first direction. When the valve is in a second orientation, the cold plate and the heat removal unit are fluidly coupled in a second configuration and the cooling fluid flows through the internal fluid pathway in a second direction.
    Type: Application
    Filed: April 11, 2023
    Publication date: July 11, 2024
    Applicant: Quanta Computer Inc.
    Inventors: Wei-Te WANG, Ming-Hung TSAI, Bo-Cheng CIOU, Jen-Mao CHEN
  • Publication number: 20240236401
    Abstract: A terminal, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: receiving an object in a live streaming; displaying the object on the terminal; detecting a keyword in the object corresponding to a function in the live streaming; and triggering the function in response to an operation on the object. The present disclosure may allow the streamers to generate or amend an object such as stickers on the live streaming room in a more flexible manner. At the same time, the viewer may perform an operation on the object to realize a corresponding function in a more convenient manner. Therefore, the interaction among streamers and viewers may be increased, and the user experience may also be enhanced.
    Type: Application
    Filed: July 3, 2023
    Publication date: July 11, 2024
    Inventors: Yu-Cheng FAN, Sz-Chi HUANG, Chih-Yuan WANG
  • Publication number: 20240234404
    Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng TZENG, Shih-Wei PENG, Ching-Yu HUANG, Chun-Yen LIN, Wei-Cheng LIN, Jiann-Tyng TZENG, Szuya LIAO, Jui-Chien HUANG, Cheng-Yin WANG, Ting-Yun WU
  • Publication number: 20240234419
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 11, 2024
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Lo Heng CHANG, CHIH-HAO WANG, Chien Ning YAO, Kuo-Cheng CHIANG
  • Publication number: 20240233282
    Abstract: An augmented reality display system includes a body, an image source device configured to output image information, an optical waveguide device configured to receive the image information, and an optical fiber array image transmission bundle. The optical fiber array image transmission bundle includes a number of optical fibers. Each optical fiber includes an input end and an output end. Each input end is coupled with a first microlens protruding outward, and each output end is coupled with a second microlens protruding outward. The image information output by the image source device is coupled into the optical fiber array image transmission bundle through the first microlenses for total reflection, and then collimated by the second microlenses and emitted directly to the optical waveguide device. An augmented reality display device having the augmented reality display system is also disclosed.
    Type: Application
    Filed: May 16, 2023
    Publication date: July 11, 2024
    Applicant: Luxshare Precision Technology (Nanjing) Co., LTD
    Inventors: Liyuan CHANG, Cheng WANG, Guojun XU
  • Publication number: 20240234302
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Publication number: 20240230739
    Abstract: A measurement device and a method of measuring a radiation pattern by using the same are provided. The measurement device includes at least one positioner configured to move a first antenna for measuring a main lobe and a back lobe of an electromagnetic wave radiated from the first antenna.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 11, 2024
    Applicants: Advanced Semiconductor Engineering, Inc., National Chung Cheng University
    Inventors: Sheng-Chi HSIEH, Chen-Chao WANG, Sheng-Fuh CHANG, Chia-Chan CHANG, Shih-Cheng LIN, Yuan-Chun LIN, Wei-Lun HSU, Kuo-Hung CHENG
  • Publication number: 20240233819
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240234501
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. The method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. The first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. The method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Jin CAI, Chih-Hao WANG
  • Publication number: 20240234401
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 18, 2023
    Publication date: July 11, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240228612
    Abstract: Provided are an anti-Nectin-4 antibody or antigen-binding fragment thereof, an antibody conjugate comprising the same, and use thereof in the manufacture of a medicament, particularly in the manufacture of a medicament for treating and/or preventing cancer.
    Type: Application
    Filed: September 9, 2021
    Publication date: July 11, 2024
    Inventors: Cheng WANG, Dengnian LIU, Fen LI, Liang XIAO, Tongtong XUE, Junyou GE, Jingyi WANG, Le LIU, Qi REN
  • Publication number: 20240234537
    Abstract: A method for manufacturing a semiconductor structure includes forming fins over a substrate. Each of the fins includes a base fin protruding from the substrate, and first semiconductor layers and second semiconductor layers alternating stacked over the base fin. The method further includes forming an isolation structure between the base fins, forming a hard mask layer over the isolation structure, and removing the second semiconductor layers, so that the first semiconductor layers and the hard mask layer are exposed in a gate trench. The method further includes forming a gate structure in the gate trench. The gate structure wraps around the first semiconductor layers and over the hard mask layer.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG
  • Publication number: 20240226489
    Abstract: A chamber adaptor and a manufacturing method thereof. The chamber adaptor includes: a housing provided with a gas inlet, a gas outlet, a chamber inlet, and a chamber outlet, where the gas inlet is configured to be removably connected to a main board device, the gas outlet is configured to be removably connected to a respiratory pathway, the chamber inlet is configured to be removably connected to an input end of a chamber for storing liquid and the chamber outlet is configured to be removably connected to an output end of the chamber, the chamber adaptor further includes a control circuit and at least one sensing apparatus, where the at least one sensing apparatus is arranged on one end of the control circuit closer to the gas outlet and extends into a gas output channel.
    Type: Application
    Filed: October 20, 2022
    Publication date: July 11, 2024
    Applicant: Telesair, Inc.
    Inventors: Hector TRUONG, Cheng WANG, Chi Wai CHOY, Bo LI, Yong LIU
  • Publication number: 20240228509
    Abstract: The present disclosure provides for compounds of Formula (I) wherein A2, A3, A4, A6, A7, A8, A15, RA, R5, R9, R10A, R10B, R11, R12, R13, R14, R16, W, X, and Y have any of the values defined in the specification, and pharmaceutically acceptable salts thereof, that are useful as agents in the treatment of diseases and conditions, including cancer. Also provided are pharmaceutical compositions comprising compounds of Formula (I).
    Type: Application
    Filed: August 3, 2023
    Publication date: July 11, 2024
    Inventors: Wilfried Braje, George Doherty, Katja Jantos, Cheng Ji, Andrew Judd, Aaron Kunzer, Anthony Mastracchio, Xiaohong Song, Andrew Souers, Gerard Sullivan, Zhi-Fu Tao, Chunqiu Lai, Andreas Kling, Frauke Pohlki, Jessee Teske, Michael Wendt, Patrick Brady, Xilu Wang, Thomas Penning, Michael Michaelides
  • Patent number: 12030821
    Abstract: A concrete interface agent relates to the technical field of concrete surface protection, an ingredient of the concrete interface agent comprises 55 to 100 parts by weight of a nano-calcium salt solution and a nano-SiO2 precursor, 0.1 to 0.4 parts by weight of a surfactant, 30 to 60 parts by weight of a silane coupling agent and 10 to 40 parts by weight of a polydimethylsilane, an ingredient of the nano-calcium salt solution comprises 2 to 5 parts by weight of a calcium hydroxide, 2 to 5 parts by weight of an acid catalyst and 200 to 500 parts by weight of an alcohol-based organic solvent, which can form a coating layer with higher hydrophobic angle on the concrete surface, reduce the water absorption of the concrete, and is not easy to crack after drying, which has more protective effect and longer service life than the existing TEOS interface agent.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: July 9, 2024
    Assignee: Qingdao University of Technology
    Inventors: Bo Pang, Zuquan Jin, Guoqing Geng, Yunsheng Zhang, Cheng Liu, Yidong Chen, Dafu Wang, Rusheng Qian
  • Patent number: 12034062
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Patent number: 12032224
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: July 9, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Sin-Hong Lin, Yung-Ping Yang, Wen-Yen Huang, Yu-Cheng Lin, Kun-Shih Lin, Chao-Chang Hu, Yung-Hsien Yeh, Mao-Kuo Hsu, Chih-Wei Weng, Ching-Chieh Huang, Chih-Shiang Wu, Chun-Chia Liao, Chia-Yu Chang, Hung-Ping Chen, Wei-Zhong Luo, Wen-Chang Lin, Shou-Jen Liu, Shao-Chung Chang, Chen-Hsin Huang, Meng-Ting Lin, Yen-Cheng Chen, I-Mei Huang, Yun-Fei Wang, Wei-Jhe Shen
  • Patent number: 12034279
    Abstract: A power conversion apparatus includes M first slots, wherein each of M first slots is electrically connected to an input side of one of N first bus bars, and a respective first slot of the M first slots is electrically connected to a first module that can supply an alternating current or a direct current to the first bus bar electrically connected to the first slot. The apparatus further includes P second slots, wherein each of the P second slots is electrically connected between an output side of one of the N first bus bars and an input side of one of second bus bars, and a respective second slot of the P second slots is electrically connected to a second module that converts an alternating current into a direct current or that converts a direct current into a direct current.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 9, 2024
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Cheng Ma, Xiaoke Ran, Hongbing Wang, Wei Guo
  • Patent number: 12033899
    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang, Kuan-Lun Cheng
  • Publication number: 20240217912
    Abstract: A method for preparing a phenoxycarboxylate includes 1) allowing a salt of a phenolic compound and a halogenated carboxylate to subject to a condensation reaction in a polar solvent under the action of a catalyst; and 2) adding an acid-containing organic solvent to the condensation reaction liquid in step 1) to perform an acidification, and purifying the precipitated halogenated inorganic salt to obtain a phenoxycarboxylate. A catalyst is added in the condensation process, which can improve the reaction rate, achieve the reaction at room temperature and high material conversion rate, and avoid the problem in the prior art that the reaction needs to be performed at high temperature, about 120° C. After the condensation reaction is completed, the salt is removed by dry filtration (an anhydrous condition) by adding a methanol hydrogen chloride solution. There is no industrial wastewater, raw materials are easily recycled, and the reaction yield is high.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 4, 2024
    Inventors: Zhiqing LI, Xiaopeng HUANG, Cheng WANG, Fujun HAN, Changtao ZHOU, Qiang LIU, Qifan WU, Quangli ZHAO