Abstract: A drive system for an industrial handling vehicle comprises an electric motor, a first pump, for example, a plunger pump, and a second pump, for example, a gear pump. The first pump is configured to provide hydraulic power for a travelling device of the industrial handling vehicle. The first pump and the travelling device are in a first hydraulic circuit. The second pump is configured to provide hydraulic power for a brake device and/or a steering device and/or a handling device of the industrial handling vehicle. The second pump, the brake device, the steering device, and the handling device are in a second hydraulic circuit isolated from the first hydraulic circuit. The electric motor is operatively coupled to both the first pump and the second pump, to drive them to operate.

Abstract: A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

Abstract: This application provides an information transmission method and apparatus. The method includes: receiving first indication information from a network device, where the first indication information indicates an association relationship between a plurality of branch networks in an artificial intelligence AI network and channel state information CSI measurement configuration information; and obtaining first quantization information based on a first branch network and channel information, where the first branch network is associated with current CSI measurement configuration information, and the first branch network belongs to the plurality of branch networks in the AI network.

Abstract: A temperature-sensitive automatic rapid gas generation fire extinguishing device is provided, including a box body; a plurality of heat absorption fire extinguishing units are placed on an inner side wall of the box body, and a first trigger unit is arranged between one of the heat absorption fire extinguishing units close to the first baffle and the inner side wall of the box body; the one of the heat absorption fire extinguishing units triggers the first baffle to move down through the first trigger unit, and a relatively closed space is formed in the box body; a plurality of gas generation fire extinguishing units are placed on an inner side wall of the box body, and a second trigger unit is arranged between one of the gas generation fire extinguishing units close to the second baffle and the inner side wall of the box body.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.

Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.

Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A distributed display method provides different parts of an application interface that are collaboratively displayed on a plurality of terminals, so that manners for collaborative display between the plurality of terminals are more flexible and richer. A first terminal displays a first interface including a first part and a second part. When the first terminal detects that a preset condition is met, the first terminal displays a second interface, where the second interface includes the first part and does not include the second part; and the first terminal notifies a second terminal to display a third interface, where the third interface includes the second part and does not include the first part.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.

Abstract: A ridge recognition substrate and a ridge recognition apparatus. The ridge recognition substrate includes: a base substrate including a photosensitive area, and a light-shielding area located on at least one side of the photosensitive area; a plurality of photosensitive devices, arranged in the photosensitive area in an array; each photosensitive device includes a first electrode, a photoelectric conversion structure and a second electrode arranged in layers, the photoelectric conversion structure is electrically connected with the first electrode, and the photoelectric conversion structure directly contacts with the second electrode; and dummy devices, arranged in the light-shielding area in an array, each dummy device including a third electrode, an equivalent dielectric layer and a fourth electrode, the third electrode and the first electrode is in the same layer, the fourth electrode is located at the side of the layer where the second electrode is located facing away from the base substrate.

Abstract: This application relates to a negative electrode plate, a secondary battery and apparatus thereof. The secondary battery of the present application comprises a negative electrode plate, the negative electrode plate comprises a composite current collector and a negative electrode active material layer disposed on at least one surface of the composite current collector, the negative electrode active material layer comprises a silicon-based active material, the silicon-based active material accounts for 0.5 wt % to 50 wt % of total mass of the negative electrode active material layer, and the composite current collector comprises a polymer support layer and a metal conductive layer disposed on at least one surface of the polymer support layer. The secondary battery and the negative electrode plate achieve good coordination between the current collector and the negative electrode active material layer.

Abstract: A method for shale gas exploitation includes performing horizontal drilling operation on an area to be constructed, forming a crack around a horizontal drill hole wall by shaped charge perforation; expanding the crack around a horizontal hole hydraulic fracturing, and extracting methane gas after a fracturing fluid is discharged; after methane gas is reduced, performing in-situ combustion explosion fracturing on the methane involved in horizontal drilling; thereafter continuing to expand the crack in the horizontal drill hole such that methane continues to seep out, and continuing extracting methane; repeating combustion explosion fracturing and extraction operations, so as to increase combustion explosion cracking permeability, and greatly enhance the exploitation effect of shale gas. The method is suitable for fracturing reconstruction of unconventional oil and gas reservoirs such as shale gas reservoirs, coal seam gas reservoirs and tight sandstone gas reservoirs.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.