Patents by Inventor Cheng-Wei Cheng

Cheng-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240407178
    Abstract: A phase-change memory cell includes an insulating layer; a first electrode embedded in the insulating layer, wherein an outer end of the first electrode is locally flush with an outer surface of the insulating layer; a second electrode, larger than the first electrode, and spaced from the first electrode; a compositionally homogenous crystalline phase change material layer; and a highly oriented seed layer. A crystal structure of the homogenous phase change material layer is correlated with a crystal structure of the highly oriented seed layer. The compositionally homogenous phase change material layer and the highly oriented seed layer are located at least partially between the first and second electrodes.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Guy M. Cohen, Cheng-Wei Cheng, Matthew Joseph BrightSky, Daniel Piatek
  • Publication number: 20240196766
    Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 13, 2024
    Inventors: Matthew Joseph BrightSky, Cheng-Wei Cheng, Guy M. Cohen, Robert L. Bruce, Asit Ray, Wanki Kim
  • Patent number: 11916130
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 27, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 11889771
    Abstract: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 30, 2024
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd.
    Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Robert L. Bruce, Martin Michael Frank, Hiroyuki Miyazoe
  • Publication number: 20230371405
    Abstract: A structure comprising a top electrode and a bottom electrode. The structure further comprises a multilayer stack disposed between the top electrode and the bottom electrode, where the multilayer stack comprises alternating confinement layers and phase-change material layers, and where at least two of the phase-change material layers have different doping concentrations of at least one dopant.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Inventors: Kevin W. Brew, JIN PING HAN, Timothy Mathew Philip, Cheng-Wei Cheng, ROBERT L. BRUCE, Matthew Joseph BrightSky
  • Patent number: 11818971
    Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Ruilong Xie, Nanbo Gong, Cheng-Wei Cheng
  • Patent number: 11723293
    Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 8, 2023
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Cheng-Wei Cheng, Matthew Joseph BrightSky
  • Publication number: 20230180636
    Abstract: A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Cheng-Wei Cheng, ROBERT L. BRUCE, Matthew Joseph BrightSky, Gloria Wing Yun Fraczak
  • Publication number: 20230047004
    Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 16, 2023
    Inventors: Heng Wu, Ruilong Xie, Nanbo Gong, Cheng-Wei Cheng
  • Patent number: 11563173
    Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: January 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Ruilong Xie, Nanbo Gong, Cheng-Wei Cheng
  • Publication number: 20220407000
    Abstract: A memory cell formed in a pillar structure between a first electrode and a second electrode includes laminated encapsulation structure. In one example, the pillar includes a body of ovonic threshold switch material, carbon-based intermediate layers, metal layers and a body of phase change memory material in electrical series between the first and second electrodes. The laminated encapsulation structure surrounds the pillar. The laminated dielectric encapsulation structure comprises at least three conformal layers, including a first layer of material, a second conformal layer of a second layer material different from the first layer material; and a third conformal layer of a third layer material different from the second layer material.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Applicants: MACRONIX INTERNATIONAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Hsiang YANG, Hsiang-Lan LUNG, Wei-Chih CHIEN, Cheng-Wei CHENG, Matthew J. BRIGHTSKY
  • Publication number: 20220310912
    Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: ROBERT L. BRUCE, Cheng-Wei Cheng, Matthew Joseph BrightSky
  • Publication number: 20220209113
    Abstract: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Robert L. Bruce, Martin Michael Frank, Hiroyuki Miyazoe
  • Publication number: 20220123209
    Abstract: A switching device having a first electrode, a second electrode, and a switching layer between the first and second electrodes, formed using a chalcogenide composition doped with an element that suppresses oxidation, which results in improved manufacturability and yield. For selector material based on AsSeGeSi or other chalcogenide materials that include selenium or arsenic, or other chalcogenide materials that include selenium or arsenic and silicon, the element added to suppress oxidation can be sulfur.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huai-Yu CHENG, I-Ting KUO, Hsiang-Lan LUNG, Cheng-Wei CHENG, Matthew J. BRIGHTSKY
  • Patent number: 11271155
    Abstract: An ovonic threshold switch comprises a thin film composed essentially of Si, Ge, Se, As, and an amount of a chalcogen that is effective to passivate oxidation of the composition in the presence of water vapor, wherein the chalcogen is selected from the list consisting of: Te and S. In one or more embodiments, the chalcogen is S. In one or more embodiments, the chalcogen is Te. In one or more embodiments, the effective amount of the chalcogen is greater than 1% by atomic percent. In one or more embodiments, the effective amount of the chalcogen is less than 10% by atomic percent. In one or more embodiments, the composition of matter comprises 10% Si, 15% Ge, 40% Se, 30% As, and 5% chalcogen by atomic percent.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 8, 2022
    Assignees: International Business Machines Corporation, MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Hsiang-Lan Lung
  • Publication number: 20210288251
    Abstract: An ovonic threshold switch comprises a thin film composed essentially of Si, Ge, Se, As, and an amount of a chalcogen that is effective to passivate oxidation of the composition in the presence of water vapor, wherein the chalcogen is selected from the list consisting of: Te and S. In one or more embodiments, the chalcogen is S. In one or more embodiments, the chalcogen is Te. In one or more embodiments, the effective amount of the chalcogen is greater than 1% by atomic percent. In one or more embodiments, the effective amount of the chalcogen is less than 10% by atomic percent. In one or more embodiments, the composition of matter comprises 10% Si, 15% Ge, 40% Se, 30% As, and 5% chalcogen by atomic percent.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Hsiang-Lan Lung
  • Publication number: 20210249521
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Application
    Filed: February 26, 2021
    Publication date: August 12, 2021
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Publication number: 20210210683
    Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Heng Wu, Ruilong Xie, Nanbo Gong, Cheng-Wei Cheng
  • Patent number: 10998420
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 10937871
    Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun