Patents by Inventor Cheng-Wei Cheng
Cheng-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10930565Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.Type: GrantFiled: November 1, 2018Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: HsinYu Tsai, Renee T. Mo, Cheng-Wei Cheng, Ko-Tao Lee
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Patent number: 10923348Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.Type: GrantFiled: May 29, 2019Date of Patent: February 16, 2021Assignee: International Business Machines CorporationInventors: Hiroyuki Miyazoe, Cheng-Wei Cheng, Sanghoon Lee
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Patent number: 10886415Abstract: A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.Type: GrantFiled: March 7, 2019Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ko-Tao Lee, Pierce I-Jen Chuang, Cheng-Wei Cheng, Seyoung Kim
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Publication number: 20200381250Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.Type: ApplicationFiled: May 29, 2019Publication date: December 3, 2020Inventors: Hiroyuki MIYAZOE, Cheng-Wei CHENG, Sanghoon LEE
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Publication number: 20200287055Abstract: A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: Ko-Tao Lee, Pierce I-Jen Chuang, Cheng-Wei Cheng, Seyoung Kim
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Patent number: 10755925Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.Type: GrantFiled: July 19, 2019Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
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Patent number: 10756506Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.Type: GrantFiled: August 7, 2019Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
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Publication number: 20200235207Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.Type: ApplicationFiled: January 24, 2020Publication date: July 23, 2020Applicant: Tessera, Inc.Inventors: Cheng-wei Cheng, Effendi Leobandung, Devendra K. Sadana
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Patent number: 10686090Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.Type: GrantFiled: September 15, 2017Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
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Publication number: 20200144123Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: HsinYu Tsai, Renee T. Mo, Cheng-Wei Cheng, Ko-Tao Lee
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Patent number: 10644018Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.Type: GrantFiled: April 12, 2018Date of Patent: May 5, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Atsuhiro Suzuki
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Patent number: 10601199Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.Type: GrantFiled: January 4, 2019Date of Patent: March 24, 2020Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
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Patent number: 10600891Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.Type: GrantFiled: March 28, 2019Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
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Patent number: 10546926Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.Type: GrantFiled: May 3, 2019Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Effendi Leobandung, Devendra K. Sadana
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Publication number: 20190363509Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
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Patent number: 10489947Abstract: A display method includes requesting a memory to allocate a first memory space for the first application corresponding to a first adjusted size adjusted from a first default size of a first destination frame of the first application, requesting the memory to allocate a second memory space for the second application corresponding to a second default size of a second destination frame of the second application, synthesizing a first application image generated in the first memory space and a second application image generated in the second memory space, and controlling a display component to display the display image.Type: GrantFiled: March 9, 2016Date of Patent: November 26, 2019Assignee: HTC CorporationInventor: Cheng-Wei Cheng
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Publication number: 20190341250Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
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Patent number: 10460937Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.Type: GrantFiled: November 7, 2017Date of Patent: October 29, 2019Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
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Patent number: 10460797Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.Type: GrantFiled: September 8, 2017Date of Patent: October 29, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
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Patent number: 10460948Abstract: A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.Type: GrantFiled: September 4, 2015Date of Patent: October 29, 2019Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu