Patents by Inventor Cheng-Wei Cheng

Cheng-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220123209
    Abstract: A switching device having a first electrode, a second electrode, and a switching layer between the first and second electrodes, formed using a chalcogenide composition doped with an element that suppresses oxidation, which results in improved manufacturability and yield. For selector material based on AsSeGeSi or other chalcogenide materials that include selenium or arsenic, or other chalcogenide materials that include selenium or arsenic and silicon, the element added to suppress oxidation can be sulfur.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huai-Yu CHENG, I-Ting KUO, Hsiang-Lan LUNG, Cheng-Wei CHENG, Matthew J. BRIGHTSKY
  • Patent number: 11271155
    Abstract: An ovonic threshold switch comprises a thin film composed essentially of Si, Ge, Se, As, and an amount of a chalcogen that is effective to passivate oxidation of the composition in the presence of water vapor, wherein the chalcogen is selected from the list consisting of: Te and S. In one or more embodiments, the chalcogen is S. In one or more embodiments, the chalcogen is Te. In one or more embodiments, the effective amount of the chalcogen is greater than 1% by atomic percent. In one or more embodiments, the effective amount of the chalcogen is less than 10% by atomic percent. In one or more embodiments, the composition of matter comprises 10% Si, 15% Ge, 40% Se, 30% As, and 5% chalcogen by atomic percent.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 8, 2022
    Assignees: International Business Machines Corporation, MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Hsiang-Lan Lung
  • Publication number: 20210288251
    Abstract: An ovonic threshold switch comprises a thin film composed essentially of Si, Ge, Se, As, and an amount of a chalcogen that is effective to passivate oxidation of the composition in the presence of water vapor, wherein the chalcogen is selected from the list consisting of: Te and S. In one or more embodiments, the chalcogen is S. In one or more embodiments, the chalcogen is Te. In one or more embodiments, the effective amount of the chalcogen is greater than 1% by atomic percent. In one or more embodiments, the effective amount of the chalcogen is less than 10% by atomic percent. In one or more embodiments, the composition of matter comprises 10% Si, 15% Ge, 40% Se, 30% As, and 5% chalcogen by atomic percent.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Hsiang-Lan Lung
  • Publication number: 20210249521
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Application
    Filed: February 26, 2021
    Publication date: August 12, 2021
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Publication number: 20210210683
    Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Heng Wu, Ruilong Xie, Nanbo Gong, Cheng-Wei Cheng
  • Patent number: 10998420
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 10937871
    Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun
  • Patent number: 10930565
    Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: HsinYu Tsai, Renee T. Mo, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 10923348
    Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Miyazoe, Cheng-Wei Cheng, Sanghoon Lee
  • Patent number: 10886415
    Abstract: A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ko-Tao Lee, Pierce I-Jen Chuang, Cheng-Wei Cheng, Seyoung Kim
  • Publication number: 20200381250
    Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventors: Hiroyuki MIYAZOE, Cheng-Wei CHENG, Sanghoon LEE
  • Publication number: 20200287055
    Abstract: A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Ko-Tao Lee, Pierce I-Jen Chuang, Cheng-Wei Cheng, Seyoung Kim
  • Patent number: 10755925
    Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10756506
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20200235207
    Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.
    Type: Application
    Filed: January 24, 2020
    Publication date: July 23, 2020
    Applicant: Tessera, Inc.
    Inventors: Cheng-wei Cheng, Effendi Leobandung, Devendra K. Sadana
  • Patent number: 10686090
    Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • Publication number: 20200144123
    Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 7, 2020
    Inventors: HsinYu Tsai, Renee T. Mo, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 10601199
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10600891
    Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Patent number: 10546926
    Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Devendra K. Sadana