Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.

Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.

Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.

Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.

Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.

Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.

Abstract: A method for use in forming a fin of a field-effect transistor includes: patterning a mandrel into a substrate at least by recessing portions of the substrate; forming dielectric material at least on the recessed portions of the substrate, wherein the dielectric material partially covers exterior sidewalls of the mandrel; forming a first buffer at least on a portion of the exterior sidewalls of the mandrel not covered by the dielectric material; forming a second buffer at least on exterior sidewalls of the first buffer; forming a semiconductor channel at least on the dielectric material, wherein at least the second buffer is between the channel and the mandrel; exposing interior sidewalls of at least the first buffer at least by removing the mandrel; and removing the first buffer and the second buffer without removing the channel.

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1?y), where 0.8<y<1, and SizGe(1?z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.

Abstract: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1?y), where 0.8<y<1, and SizGe(1?z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.