Patents by Inventor Cheng-Wei Cheng

Cheng-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Epitaxial lift-off process with guided etching
    Patent number: 9653308
    Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu
  • Integrated Circuit With Heterogeneous CMOS Integration Of Strained Silicon Germanium And Group III-V Semiconductor Materials And Method To Fabricate Same
    Publication number: 20170125445
    Abstract: A structure includes an off axis Si substrate with an overlying s-Si1?xGe, layer and a BOX between the off-axis Si substrate and the s-Si1?xGex layer. The structure further includes pFET fins formed in the s-Si1?xGex layer and a trench formed through the s-Si1?xGe, layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1?xGex layer has a value of x that results from a condensation process that merges an initial s-Si1?xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 4, 2017
    Inventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
  • III-V PHOTONIC INTEGRATED CIRCUITS ON SILICON SUBSTRATE
    Publication number: 20170125970
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Reduced current leakage semiconductor device
    Patent number: 9627482
    Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun
  • INTEGRATED CIRCUIT WITH HETEROGENEOUS CMOS INTEGRATION OF STRAINED SILICON GERMANIUM AND GROUP III-V SEMICONDUCTOR MATERIALS AND METHOD TO FABRICATE SAME
    Publication number: 20170104012
    Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1-xGex layer and a BOX between the off-axis Si substrate and the s-Si1-xGex layer. The structure further includes pFET fins formed in the s-Si1-xGex layer and a trench formed through the s-Si1-xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1-xGex layer has a value of x that results from a condensation process that merges an initial s-Si1-xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 13, 2017
    Inventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
  • III-V MOSFET WITH SELF-ALIGNED DIFFUSION BARRIER
    Publication number: 20170092722
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Application
    Filed: April 22, 2016
    Publication date: March 30, 2017
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • ASYMMETRIC III-V MOSFET ON SILICON SUBSTRATE
    Publication number: 20170092763
    Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo, Yanning Sun
  • III-V MOSFET WITH SELF-ALIGNED DIFFUSION BARRIER
    Publication number: 20170092727
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Polarization free gallium nitride-based photonic devices on nanopatterned silicon
    Patent number: 9608160
    Abstract: After forming patterned dielectric material structures over a (100) silicon substrate, portions of the silicon substrate that are not covered by the patterned dielectric material structures are removed to provide a plurality of openings within the silicon substrate. Each opening exposes a surface of the silicon substrate having a (111) crystalline plane. A buffer layer is then formed on the exposed surfaces of the patterned dielectric material structures and the silicon substrate. A dual phase Group III nitride structure including a cubic phase region is formed filling a space between each neighboring pair of the patterned dielectric material structures and one of the openings located beneath the space. Finally, at least one Group III nitride layer is epitaxially deposited over the cubic phase region of the dual phase Group III nitride structure.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Cheng-Wei Cheng, Tayfun Gokmen, Ning Li, John A. Ott, Devendra K. Sadana, Kuen-Ting Shiu
  • COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIAL SEMICONDUCTOR MATERIAL FORMED USING LATERAL OVERGROWTH
    Publication number: 20170075062
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • III-V photonic integrated circuits on silicon substrate
    Patent number: 9595805
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Stress Assisted Wet and Dry Epitaxial Lift Off
    Publication number: 20170069491
    Abstract: A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth
    Patent number: 9590393
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING
    Publication number: 20170062232
    Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu
  • SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS
    Publication number: 20170053796
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Application
    Filed: November 3, 2016
    Publication date: February 23, 2017
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Preparation of low defect density of III-V on Si for device fabrication
    Patent number: 9570296
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Enhanced defect reduction for heteroepitaxy by seed shape engineering
    Patent number: 9564494
    Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser
  • METAL PARTICLE ENHANCED FORSTER RESONANCE ENERGY TRANSFER FOR ORGANIC OPTOELECTRONIC DEVICE
    Publication number: 20170033305
    Abstract: A photovoltaic device that includes an organic or quantum dot sensitizer layer for absorbing light spectra and providing excitons. The sensitizer layer may include metal particles embedded therein for increased exciton transfer efficiency. The photovoltaic device may further include a junction comprising an electron donor layer and electron acceptor layer for charge carrier transport.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, Ning Li, Kuen-Ting Shiu
  • PREPARATION OF LOW DEFECT DENSITY OF III-V ON SI FOR DEVICE FABRICATION
    Publication number: 20170025504
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Application
    Filed: October 7, 2016
    Publication date: January 26, 2017
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Keun-Ting Shiu, Yanning Sun
  • Asymmetric III-V MOSFET on silicon substrate
    Patent number: 9553166
    Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo, Yanning Sun