Abstract: A corrosion positioning system, a corrosion inspection vehicle and a corrosion positioning method using the same are provided. The corrosion positioning method includes the following steps. An image information is read by a corrosion hotspot recognition module to recognize a corrosion hotspot. A location information of the corrosion hotspot is obtained by a corrosion hotspot positioning module. The location information of the corrosion hotspot is corrected by an inspection optimization module to obtain a corrected location information. The step of correcting the location information of the corrosion hotspot includes the following steps. The correlation information of a plurality of feature points in a plurality of frames in the image information is analyzed by the inspection optimization module. The position information of a point to be corrected is corrected by the inspection optimization module according to the correlation information.

Abstract: Expandable vascular introducer sheath devices, systems and method for low profile delivery, expansion to accommodate intravascular devices, and recovery for subsequent removal. The expandability features may be incorporated into other intravascular devices such as guide extension catheters, thrombus removal devices, etc.

Abstract: A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: A memory device includes a first signal line, a second signal line, a first memory cell, a second memory cell, a third memory cell and a fourth memory cell. The first memory cell is coupled to the first signal line. The second memory cell has a first terminal coupled to the first signal line through the first memory cell and a second terminal coupled to the second signal line. The third memory cell is coupled to the first signal line. The fourth memory cell is coupled to the first signal line through the third memory cell, wherein a parasitic capacitance of the fourth memory cell is isolated from the second memory cell through the third memory cell.

Abstract: A shaft voltage reduction structure is mounted on an electric machine having a bearing house and a rotor shaft rotatably connected together, and includes an electrically conductive main body, at least one electrically conductive bearing, and an electrically conductive shaft. The conductive main body is mounted to a bottom of the bearing house and includes a conductive shaft barrel projected from a center thereof. The conductive shaft barrel internally defines a shaft receiving hole, in which the conductive bearing is received. The conductive shaft includes a connecting end and a pivotal end connected to the rotor shaft and the shaft receiving hole, respectively. A shaft voltage across the rotor shaft of the electric machine is guided by the conductive shaft to release in a closed loop formed among the conductive main body, the conductive bearing and the bearing house, so as to reduce the shaft voltage of the electric machine.

Abstract: Disclosed is an inductive coupling system and method for adaptive control of power transfer for a wireless three-dimensional stacked chip package. The system includes a slave chip and a master chip connected via inductive coupling; the system for adaptive control of power transfer herein shifts a load feedback voltage received by the slave chip into a feedback voltage data codeword through a level decision circuit, and the system can load the feedback voltage data codeword onto a data link of the system and feedback same to the master chip. In the present disclosure, the master chip includes a DPID control circuit controls a voltage-controlled oscillator and a frequency divider to adjust the frequency of an input clock in an energy transfer system so as to achieve adaptive control of the transmitting power of a transmitting chip.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Abstract: The present disclosure relates to a visual game editor system comprising a game editor, a conversion module and a script editing module. The game editor is used by a creator to design and build a game content. The conversion module is used to provide a proprietary game data format through which the conversion module converts the game content to a proprietary game format to fit different game platforms. The script editing module is used to provide an event-based script editor, which allows the creator to edit the game content by setting conditions and values in plain text through the event-based script editor of the script editing module. In this disclosure, the game editor writes the game content in a non-programmable way.

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

Abstract: A crystal resonator includes a crystal plate and an electrode set. The crystal plate includes a first vibration section and a second vibration section arranged along an oscillating direction, and exhibits a thickness shear mode. The electrode set includes a first electrode pair disposed on the first vibration section, and a second electrode pair disposed on the second vibration section. The first electrode pair and the second electrode pair are configured to apply the applied voltages with opposite electrical polarities to the first vibration section and the second vibration section, respectively, which causes the first vibration section and the second vibration section to dynamically deform in the thickness shear mode along the oscillating direction, and do out of phase motion with respect to each other.

Abstract: An electrical connector structure, adapted for connecting an optoelectronic transceiver module on a mainboard, includes an interposer module and a fixing structure. The interposer module includes a first board and a second board assembled with each other, and at least a terminal module. A first terminal arm of the terminal module extends out of the first board, and a second terminal arm extends out of the second board. The fixing structure includes a pair of fixing walls, a plurality of first limiting members, and a second limiting member. The interposer module and the optoelectronic transceiver module are detachably arranged on the fixing structure and located on the mainboard, and the first limiting members press the second board, and the second limiting member presses the optoelectronic transceiver module, which in turn shortens a signal transmission path.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: The disclosure provides a preparation method of an impact-resistant polyester composition, which is a continuous process and includes the following steps. A recycled release film is crushed, compacted and dried, and then melted, extruded and degassed. The recycled release film contains a recycled PET resin. After filtration, a liquid viscosifying system is used for thickening. Next, it is melted and kneaded, modified with modifiers and extruded. The modifiers include impact modifiers, compatibilizers, antioxidants and lubricants. After the rubber strips are cooled with water, they are then pelletized and dehydrated to produce the impact-resistant polyester composition.

Abstract: The disclosure provides a preparation method of polyester material, which is a continuous process and includes the following steps. A recycled release film is crushed, compacted and dried, and then melted, extruded and degassed. After filtration, a liquid viscosifying system is used for thickening. After that, it is melted and kneaded, modified with modifiers and extruded, and then pelletized and dehydrated to make the polyester material, wherein the modifiers include nucleating agents, lubricants and antioxidants.

Abstract: A device includes a dielectric pattern, a first dielectric layer, a stack and a conductive pillar. The first dielectric layer is disposed on the dielectric pattern, wherein a material of the dielectric pattern is different from a material of the first dielectric layer. The stack is disposed on the first dielectric layer. The conductive pillar extends along the stack, wherein the conductive pillar penetrates through the first dielectric layer and disposed on the dielectric pattern.