Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.

Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

Abstract: Disclosed are a control method for focus movement on an EPG user interface and a display device. The method includes: displaying a television broadcast program on a display screen; receiving an instruction for displaying an EPG user interface, and displaying the EPG user interface on the display screen in response to the instruction; and receiving an instruction for indicating the movement of a focus along a channel arrangement direction in the EPG user interface, and in response to the instruction, determining a new position to which the focus moves in a target television channel according to the position of a pre-selected reference broadcast program, so as to control the focus to move to a target broadcast program corresponding to the new position.

Abstract: A semiconductor quantum dot structure includes a core and a shell. The core includes a seed crystal made of a first compound M1C1, a core layer, and a barrier layer grown in such order. The seed crystal has first regions that are inactive with oxygen, and second regions that are easily reactive with oxygen. The core layer is made of the first compound M1C1, and has first and second areas. Each of the first areas is positioned on a corresponding one of the first regions. Each of the second areas is positioned on a corresponding one of the second regions. Each of the first areas has a thickness greater than that of each of the second areas. The barrier layer is made of a second compound selected from M1X1 and X2C1. The shell is grown on the barrier layer, and is made of a third compound M2C2.

Abstract: A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: A display panel and a preparation method thereof are provided. A first display region and a second display region are defined on the display panel, and the display panel includes: a substrate, a driving device layer, and a light-emitting device layer. In the second display region, the driving device layer is further provided with a dummy through hole located within an orthographic projection range of at least one of the light-emitting subpixels on the substrate, and the dummy through hole and the at least one light-emitting subpixel are insulated from each other. The display panel can ensure the electrical uniformity between thin film transistors (TFTs) in the second display region, thereby alleviating non-uniform display.

Abstract: Additive manufacturing (AM) methods and devices for high-melting-point materials are disclosed. In an embodiment, an additive manufacturing method includes the following steps. (S1) Slicing a three-dimensional computer-aided design model of a workpiece into multiple layers according to shape, thickness, and size accuracy requirements, and obtaining data of the multiple layers. (S2) Planning a forming path according to the data of the multiple layers and generating computer numerical control (CNC) codes for forming the multiple layers. (S3) Obtaining a formed part by preheating a substrate, performing a layer-by-layer spraying deposition by a cold spraying method, and heating a spray area to a temperature until the spraying deposition of all sliced layers is completed. (S4) Subjecting the formed part to a surface modification treatment by a laser shock peening method.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

Abstract: A display panel and a display device are provided. The display panel includes a first display area and a second display area, the first display area is provided with a plurality of first pixel repeating units disposed in array, and the second display area is provided with a plurality of second pixel repeating units disposed in array, wherein a quantity of the first light-emitting units included in the first pixel repeating unit is equal to a quantity of the second light-emitting units included in the second pixel repeating unit, and an area of the first pixel repeating unit is smaller than an area of the second pixel repeating unit.

Abstract: The present disclosure provides an electronic device and a display panel. The display panel includes a transition display region and a transparent display region. First pixel driving circuits are placed in the transition display region. Dummy pixel driving circuits are placed in the transition display region. One of the dummy pixel driving circuit is adjacently placed within a predetermined distance from at least one side of the first pixel driving circuits arranged along the second direction. This could reduce the environment difference between the pixel driving circuit close to the light sensing region and the pixel driving circuit inside the transition display region and thus reduce the luminance difference between the first display pixels controlled by the pixel driving circuit close to the light sensing region and the first display pixels controlled by the pixel driving circuit inside the transition display region.

Abstract: A central routing function (CRF) comprises back-to-back user agent application that receives a request for a call route list from a network element, wherein the request comprises a destination telephone number, a list generation application that obtains the call route list from the prioritized call route lists stored in the non-transitory memory based on the destination telephone number, wherein the call route list comprises a plurality of addresses, a pseudo domain name service (DNS) application that translates each address in the call route list into an Internet Protocol (IP) address, in which the back-to-back user agent application attempts to terminate a call using the IP address in the call route list, and in which the CRF platform is implemented in a software container.

Abstract: The present invention utilizes a high-speed intensive mixer in a fluidizing-type, solid-phase, neutralization reactor to blend solid-state alkali hydroxide with any humic acid sources. The final product is a dry humic acid salt. The purpose of this innovative method is to eliminate a series of complicated unit operations commonly employed by the traditional process. These removed steps may include dissolving caustic soda, mixing in a paste-like formation, extrusion, granulation, drying, and grinding, etc. The invention contributes to a simplified flowsheet, resulting in sharply reduced equipment investment, plant space, and labor and energy costs. All of these factors coupled with increased productivity will drastically lower the overall production cost. Also, the reduction of dust pollution will greatly minimize the impact in environmental protection and safety issues.

Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.

Abstract: The present application discloses a display panel and a display device. The display panel includes substrate, a plurality of pixel driving circuits, and a light-shielding layer. By disposing the light-shielding layer in a transition display region of the display panel, disposing the light-shielding layer between the substrate and an active layer of each of transistors of the pixel driving circuits, and configuring an orthographic projection of light-shielding portions on the substrate to cover an orthographic projection of overlapping portions on the substrate, the light-shielding layer can shield infrared light emitted by the transmitting sensor, thereby preventing the transistors from an interference of the infrared light.