Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: A data processing system includes: a processor; a memory containing programming instructions for execution by the processor; and a network interface for communicating with an Artificial Intelligence (AI) engine. The programming instructions include an application for generating written content, the application having a function to generate and submit a structured query regarding the written content to the AI engine to generate feedback on an assessed quality of the written content, the structured query structured to prompt for feedback in a variety of specified categories for the written content. The application further includes a user interface to display the feedback on the written content and provide an option to a user to implement the feedback to revise the written content.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: A ratchet wrench assembly is provided that includes a head, a ratchet gear, a yoke, one or more drive pins, a body, and a ratchet pawl. The body may include one or more drive edges and a fastener drive member. A first drive edge may be engaged with a first drive pin such that reciprocation of the yoke causes rotation of the body and the fastener drive member about the axis of rotation via engagement of the first drive pin between the inner surface of the yoke ring and the first drive edge. The ratchet pawl may include a first ratchet tooth configured ratchet against gear teeth of the ratchet gear to permit movement of the body relative to the head in a first rotational direction and engage the gear teeth to prevent movement of the body relative to the head in second, opposite rotational direction.

Abstract: The present disclosure relates to a finite control set model predictive control method of an LLCL battery energy storage converter, wherein the method uses a finite control set model predictive control method to control an energy storage converter based on an LLCL filter, establishes and discretizes a state space mathematical model of the LLCL battery energy storage converter to obtain a discrete model, converts reference values of a current at a grid side into reference values of a current at a converter side and a capacitor voltage based on a phasor method at the same time, defines a cost function, compares an output result of a prediction model with the reference value, selects an optimal voltage vector and selects a most appropriate switching state to work.

Abstract: A matte polyester film and a method for manufacturing the same are provided. The method for manufacturing the matte polyester film includes: providing a recycled polyester material; physically regenerating a part of the recycled polyester material to form physically regenerated polyester chips having a first intrinsic viscosity; chemically regenerating another part of the recycled polyester material to form chemically regenerated polyester chips having a second intrinsic viscosity less than the first intrinsic viscosity; mixing matte regenerated polyester chips, the physically regenerated polyester chips, and the chemically regenerated polyester chips according to a predetermined intrinsic viscosity so as to form a polyester masterbatch material; melting and then extruding the polyester masterbatch material to obtain the matte polyester film having the predetermined intrinsic viscosity.

Abstract: The present disclosure discloses an engineered liposome with cell membrane proteins to reduce melanosome transport and a preparation method thereof, and belongs to the technical field of cosmetics and biomedicine. The present disclosure provides the engineered liposome with cell membrane proteins to reduce melanosome transport and the preparation method thereof, which is easy to operate, requires no large-scale equipment, has few additives, and a preparation process is simple and environmentally friendly. The biomimetic liposome can significantly inhibit melanin transport. The fluorescence intensity of melanosomes in keratinocytes is found to decrease by 3.5-fold in a co-culture test of melanocytes and the keratinocytes, indicating that this biomimetic liposome is very effective in inhibiting accumulation of melanin in skin keratinocytes.

Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

Abstract: A semiconductor integrated circuit, a semiconductor device and a method for aligning semiconductor integrated circuits are provided. The semiconductor integrated circuit includes a substrate and an overlay mark structure in the substrate. The overlay mark structure includes first overlay marks and second overlay marks separated from each other. A first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks.

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

Abstract: A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.

Abstract: A coding apparatus and a coding method are proposed. The coding apparatus includes a memory and a processor. The processor is configured to obtain a feature map, perform lossy compression on the feature map to generate a lossy feature map, perform lossless compression on the lossy feature map to generate a resultant feature map, and store the resultant feature map in the memory.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: Oxazolidinones having structures represented by structural formula I, preparation methods therefor, and pharmaceutical uses thereof, in particular an application of said compounds and salts or compositions thereof in the treatment of a bacterial infection. In the formula: R1 is a methyl group, an ethyl group, a propyl group, a cyclopropyl group, or a vinyl group; R2 is F; and R3 is F, CH3, C2H5, CF3, CHF2, CH2F, or a cyclopropyl group.

Abstract: Provided are a method and an apparatus for gray scale measurement. The method may include: a first part of gray scale data of an LED screen is collected when the LED screen is displaying an image; a type of a chip used for driving the LED screen is determined; and a second part of gray scale data of the LED screen is predicted based on the type of the chip and the first part of gray scale data.

Abstract: An example electronic device includes a network communication interface to connect to a conference server, a central control device communication interface to connect to a local central control device, a microphone and a processor. The processor is to receive audio at the microphone and send the audio to the local central control device and to the conference server. The processor is to send the audio to the local central control device such that it is received by a nearby electronic device before the audio is received from the conference server by the nearby electronic device.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.