Abstract: An electronic device includes a display panel and a cover plate disposed relative to the display panel. The display panel has a display area and a peripheral area adjacent to the display area. The cover plate includes a substrate. The cover plate includes a light-shielding structure disposed on the surface of the substrate. The light-shielding structure includes a first portion corresponding to the display area. The cover plate includes an anti-reflective layer disposed on another surface of the substrate. The anti-reflective layer corresponds to the display area and the peripheral area. The penetration rate of the portion of the cover plate that corresponds to the display area is in a range of 20% to 92%.

Abstract: One embodiment of the present invention sets forth a technique for combining a source image and a driver image. The technique includes determining a first region of the source image to be blended with the driver image. The technique also includes inputting a second region of the source image that lies outside of the first region and the driver image into a neural network. The technique further includes generating, via the neural network, an output image that includes a third region corresponding to the first region of the source image and a fourth region corresponding to the second region of the source image, where the third region includes visual attributes of the driver image and a context associated with the source image and the fourth region includes visual attributes of the second region of the source image and the context associated with the source image.

Abstract: A wire bonding structure and a manufacturing method thereof are provided. The wire bonding structure is suitable for chip packaging devices. The wire bonding structure includes a wire bonding pad layer, a metal layer and a buffer layer. The metal layer contacts and is underneath the wire bonding pad layer. The buffer layer contacts and is underneath the metal layer. The buffer layer has plural through holes spaced apart from each other. The through holes penetrate the buffer layer from top to bottom and correspondingly define plural low dielectric constant material blocks and plural air gaps that are laterally interleaved with each other in the cross-sectional direction.

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

Abstract: A data processing system includes: a processor; a memory containing programming instructions for execution by the processor; and a network interface for communicating with an Artificial Intelligence (AI) engine. The programming instructions include an application for generating written content, the application having a function to generate and submit a structured query regarding the written content to the AI engine to generate feedback on an assessed quality of the written content, the structured query structured to prompt for feedback in a variety of specified categories for the written content. The application further includes a user interface to display the feedback on the written content and provide an option to a user to implement the feedback to revise the written content.

Abstract: A cloud application-based resource transfer method, apparatus, computer device and storage medium. The method includes: displaying, through a cloud application, a video interface generated after processing through a cloud; displaying, in response to a trigger operation on a target visual element in the video interface used for triggering resource transfer, a resource transfer channel interface generated by the cloud; displaying a target resource transfer channel in the resource transfer channel interface; displaying resource transfer-related information corresponding to the target resource transfer channel and generated by the cloud; and triggering, in response to a resource transfer confirmation operation for the resource transfer-related information, a resource transfer operation that is based on the resource transfer-related information through the target resource transfer channel.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: A urine collecting and analyzing apparatus for a toilet, the apparatus including a housing with a seat riser that mounts to the toilet rim and a measurement chamber that extends downwardly into the bowl, a urine collecting basin, a flushing system to clean the apparatus, and a controller for data processing and transmission. The basin has a bowl shape to collect urine for testing and is composed of two side panels or two side panels and a front panel. The panels are moved between a storage position along the housing and a collecting position forming the basin by a motorized mechanism. A transfer tube with a flow rate sensor and pump connects the basin to the measurement chamber. The flushing system feeds water through a flushing tube into the basin through an array of nozzles and cleans the entire surface of the basin.

Abstract: The disclosure provides a preparation method of a polyester material, which is a continuous process and includes the following steps. A recycled release film is crushed, compacted and dried, and then melted, extruded and degassed. After filtration, a liquid viscosifying system is used for thickening. After that, it is melted and kneaded, modified with modifiers and extruded, and then pelletized and dehydrated to make the polyester material, wherein the modifiers include nucleating agents, flame retardants, antioxidants, rod-shaped filling reinforcements and compatibilizers.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: A temperature-controllable test device for cable monitoring includes a vertical plate. The lower end of the vertical plate is secured to a base plate. A second motor is mounted on the rear side of the vertical plate. The output shaft end of the second motor extends to the front side of the vertical plate. A mounting plate is secured to the output shaft end of the second motor. A stretching mechanism is disposed inside the mounting plate and configured to stretch a cable. The stretching mechanism includes a transmission cavity formed inside the mounting plate. A first bidirectional reciprocating screw rod is rotatably connected between the left inner wall of the transmission cavity and the right inner wall of the transmission cavity. A turbine is mounted in the middle of the first bidirectional reciprocating screw rod.

Abstract: A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a semiconductor channel layer, a gate dielectric layer, a source terminal and a drain terminal. The semiconductor channel layer is disposed over and above the gate. The gate dielectric layer is disposed between the gate and the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. A contact plug is disposed on at least one of the source terminal and the drain terminal. A dielectric pattern surrounds the contact plug and covers the source terminal and the drain terminal. A gas barrier layer is disposed on the dielectric pattern and surrounding the contact plug.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A semiconductor device includes a substrate, an isolation feature disposed on the substrate, first and second fins protruding from the substrate and upwardly through the isolation feature, and a gate stack engaging each of the fins. The semiconductor device also includes a first epitaxial layer having a first portion over top and sidewall surfaces of S/D regions of the first fin and a second portion over top and sidewall surfaces of S/D regions of the second fin, a second epitaxial layer having a first portion over top and sidewall surfaces of the first portion of the first epitaxial layer and a second portion over top and sidewall surfaces of the second portion of the first epitaxial layer. The first and second portions of the second epitaxial layer are spaced apart. Each of the first and second portions of the second epitaxial layer is in physical contact with the isolation feature.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

Abstract: A device includes a first conductive feature, an etch stop layer, a plurality of stacks, a first conductive pillar and dielectric patterns. The etch stop layer is disposed on the first conductive feature. The stacks are disposed on the etch stop layer. The first conductive pillar extends between opposite surfaces of the stacks. The dielectric patterns are disposed at opposite sidewalls of a portion of the first conductive pillar in the etch stop layer.

Abstract: Provided is a radiative cooling substrate, sequentially composed of a broadband radiation absorption layer, a metal substrate, and a wavelength-selective infrared emission layer. Also provided is a method for preparing the aforementioned radiative cooling substrate, which simply involves placing the metal substrate into an electrophoresis tank and depositing the broadband radiation absorption layer and the wavelength-selective infrared emission layer on the two sides of the metal substrate, respectively. Additionally, a radiative cooling device, comprising the above-mentioned radiative cooling substrate, is also provided.

Abstract: The present application discloses an electric heater, a thermal management system, an electric vehicle, and an energy storage system, wherein the electric heater comprises a heating cavity assembly, the heating cavity assembly comprises a cavity cover plate, a cavity bottom plate and a fin plate arranged between the cavity cover plate and the cavity bottom plate, the fin plate includes a plurality of flow channel areas spaced from each other, and the cavity cover plate is provided with spaced isolation grooves corresponding to the interval of the flow channel areas. In the present application, the isolation grooves can be used to accurately position the corresponding flow channel areas, thereby ensuring accurate positioning of the fin plate relative to the cavity cover plate and the cavity bottom plate before performing fixed connection. In addition, since the isolation grooves may act as reinforcing ribs on the cavity cover plate, the overall rigidity of the heating cavity assembly can be improved.