Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: The present invention relates to the technical field of chip package, in particular to a semiconductor package injection molding mold, a semiconductor package injection molding device and a semiconductor package injection molding method. The semiconductor package injection molding mold includes a bottom mold and a top mold. The upper surface of the bottom mold is fitted with the lower surface of a substrate to form a semiconductor package structure; the top mold is matched with the bottom mold; the top mold has a cavity; the cavity is oriented toward the upper surface of the substrate and is used to accommodate a plastic package layer formed on the upper surface of the substrate; through holes that penetrate through the bottom mold are formed at positions corresponding to the substrate in the bottom mold; and the through holes are connected with an external pressure source.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

Abstract: An abnormal detection circuit is provided. The abnormal detection circuit includes a conversion circuit, a voltage detection circuit, and a warning circuit. The conversion circuit receives a three-phase alternating current (AC) power and converts the three-phase AC power into a driving power. The voltage detection circuit detects each phase of the three-phase AC power. When a voltage value of at least one phase AC power of the three-phase AC power is abnormal, the voltage detection circuit uses the driving power to output at least one control signal corresponding to the abnormality. The warning circuit is driven by receiving the driving power and outputs at least one warning signal corresponding to the abnormality in response to the at least one control signal.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: Provided is a functional edible oil (FEO), a preparation method therefor and use thereof. The FEO is prepared by ternary transesterification of medium-chain triglycerides (MCTs), oils rich in linoleic acid, and oils rich in linolenic acid. The fatty acid composition and distribution of the FEO were determined and optimized via comparative analysis of indexes such as melting point, and effect of improving glucose and lipid metabolism as determined by animal tests. The FEO has a mass ratio of 2.3 to 4.0 for medium chain fatty acids (MCFAs) in MCTs to long chain fatty acids (LCFAs) in the oils rich in linoleic acid, and oils rich in linolenic acid and a mass ratio of 0.5 to 1.0 for linoleic acid to linolenic acid in the LCFAs, by mass of fatty acids. The FEO is added to food products at ?18.00%.

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a plurality of auxiliary pixel driving circuits. Each of the auxiliary pixel driving circuits includes transistors, and each of the transistors includes an active layer and an insulation layer. The display panel is defined with first dummy holes in a transition display area, and the first dummy holes penetrate a part of the insulation layer away from the active layer in order to reduce difference in electrical properties between the auxiliary pixel driving circuits through the first dummy holes, thereby achieving display uniformity of the display panel.

Abstract: A director plate retainer of a fluid injector includes an outer wall which is annular in shape and which extends from an outer wall first end to an outer wall second end and which is centered about an axis. The director plate retainer also includes a lateral wall which is annular in shape and which extends toward the axis from a radially outer extent, which is proximal to the outer wall, to a radially inner extent, which is distal from the outer wall. The director plate retainer also includes an inner wall which is annular in shape and which extends from an inner wall first end, which is proximal to the lateral wall, to an inner wall second end, which is distal from the lateral wall, the inner wall extending along the axis in a direction that is opposite from the outer wall.

Abstract: A heat sealable polyester film and a method for manufacturing the same are provided. The heat sealable polyester film is made from a recycled polyester material. The heat sealable polyester film includes a base layer and a heat sealable layer formed on at least one surface of the base layer. The heat sealable layer is formed from a first polyester composition. A main component of the first polyester composition is regenerated polyethylene terephthalate and the first polyester composition further includes at least one of 1,4-butanediol, isophthalic acid, neopentyl glycol, and polybutylene terephthalate. A heat sealing temperature of the heat sealable polyester film ranges from 120° C. to 230° C.

Abstract: The application discloses a correction method, correction device and correction system for free full-screen splicing. According to the application, influence of reasons such as an external light source and a camera angle is eliminated based on curved surface simulation over color information data of multiple pixels, so that free full splicing may be implemented when a spliced display screen, after being used, is disassembled and transferred to another site for re-splicing.

Abstract: A 3D display system and a 3D display method are provided. The 3D display system includes a 3D display, a memory, and a processor. The processor is coupled to the 3D display and the memory and is configured to execute the following steps. As a first type application program is executed, an image content of the first type application program is captured, and a stereo format image is generated according to the image content of the first type application program. The stereo format image is delivered to a runtime complying with a specific development standard through an application program interface complying with the specific development standard. A display frame processing associated with the 3D display is performed on the stereo format image through the runtime, and a 3D display image content generated by the display frame processing is provided to the 3D display for displaying.

Abstract: An electronic device includes a substrate, a plurality of flexible circuit boards, a plurality of ICs and an insulator. The flexible circuit boards are disposed on the substrate. In a top view of the electronic device, the flexible circuit boards are overlapped with an edge of the substrate. The ICs are disposed on the substrate. The insulator is disposed on the flexible circuit boards and contacted the ICs, wherein the insulator has a first side and a second side opposite to the first side and the first side is closer to the edge than the second side. Along a first direction perpendicular to an extension direction of the edge, a first minimum distance between the second side and one of the ICs is less than a second minimum distance between the second side and one of the flexible circuit boards.

Abstract: This application provides an information transmission method and apparatus. The method includes: receiving first indication information from a network device, where the first indication information indicates an association relationship between a plurality of branch networks in an artificial intelligence AI network and channel state information CSI measurement configuration information; and obtaining first quantization information based on a first branch network and channel information, where the first branch network is associated with current CSI measurement configuration information, and the first branch network belongs to the plurality of branch networks in the AI network.

Abstract: This application provides a method. The method may include: a transmit-side device determines frequency-domain positions of reference signals that are used for phase noise estimation and that are on a plurality of resource blocks, where there are a plurality of reference signals on at least one resource block in the plurality of resource blocks, the reference signals occupy consecutive frequency-domain resources on the at least one resource block, for example, occupy a plurality of consecutive subcarriers; the transmit-side device maps, based on the frequency-domain positions of the reference signals on the plurality of resource blocks, the reference signals to one or more symbols, and sends, to a receive-side device, the one or more symbols to which the reference signals are mapped; and the receive-side device performs phase noise estimation based on the reference signals.