Abstract: A resin composition includes ABS resin and modified polyester resin, where the modified polyester resin includes a polyester material, a compatibilizer, a toughening agent, a crystallization inhibitor, a slip agent, and an antioxidant. The compatibilizer includes PP-MA, PE-MA, ABS-MA, E-MA-GMA, E-VA-GMA, POE-GMA, PE-GMA, ABS-GMA, or combinations thereof. The toughening agent includes POE, MBS, PTW, or combinations of the above. The crystallization inhibitor includes IPA copolyester, IPA and CHDM copolyester, PETG, PCTG, or combinations of the above. The slip agent includes stearate, polyethylene wax, modified silicone, fluororesin, or combinations thereof. The antioxidant includes a hindered phenolic antioxidant, a phenolic antioxidant, a phosphite antioxidant, or combinations of the above.

Abstract: A charging state analysis method of an electric vehicle based on electrical characteristic sequence analysis is provided. The method includes following steps: step S1, obtaining voltage sampling data and current sampling data of the electric vehicle during charging; step S2, setting a time interval, so as to divide the voltage sample data and the current sampling data obtained in step S1 into multiple data sets; step S3, calculating an electrical characteristic vector of each time interval; step S4. adding the calculation results of Step S3 to a temperature sensing value T, and generate an electrical characteristic sequence of whole charging cycle; step S5, inputting the electrical characteristic sequence of the electric vehicle into a trained TRNN in sequence to obtain corresponding results; if the result is 1, it is normal; if the result is 0, it is abnormal.

Abstract: In an example, an electronic device may include a network interface device having a first transceiver to communicate via a short-range wireless communication protocol and a second transceiver to communicate via the short-range wireless communication protocol. Further, the electronic device may include a processor connected to the network interface device. During operation, the processor may receive a request to search a first device in accordance with the short-range wireless communication protocol. Further, the processor may search a first radio frequency channel via the first transceiver to detect the first device. Furthermore, the processor may search a second radio frequency channel via the second transceiver to detect the first device. The first radio frequency channel and the second radio frequency channel may be searched in parallel.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A method for calculating a surface relaxation rate of a shale includes: a relaxation time T distribution curve and a pore throat radius r distribution curve are obtained through experiments; abscissas of the two distribution curves are standardized, and the abscissa of the relaxation time T distribution curve is expanded or shrunk to ensure an abscissa value corresponding to a maximum ordinate value in the transformed relaxation time T distribution curve is same as an abscissa value corresponding to a maximum ordinate value in the pore throat radius r distribution curve; straight lines with a number of N parallel to a y-axis of a combined curve graph including the two distribution curves are drawn and a ? value corresponding to each straight line is calculated; and ? value with the number of N are processed to obtain a final surface relaxation rate ??.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A method and system for providing tone detection for a content may include receiving a request to detect a tone for a content, retrieving user data and data about the content, detecting a content environment for the content based on at least one of the user data and the data about the content, detecting the tone for the content based on the content and the content environment, inputting the content and the detected tone into a machine-learning (ML) model for modifying the tone from the detected tone to a modified tone, obtaining at least one rephrased content segment as an output from the ML model, the rephrased content segment modifying the tone of the content from the detected tone to the modified tone, and providing at least one of the detected tone or the at least one rephrased content segment for display.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking 10 structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

Abstract: A polyester film includes a first layer, a second layer, and a third layer. The first layer includes a first recycled material. The second layer includes a second recycled material. Both the first recycled material and the second recycled material are a PET bottle recycled material. The third layer is disposed between the first layer and the second layer. The third layer includes a third recycled material, and the third recycled material includes a release film recycled material.

Abstract: A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.

Abstract: A manufacturing method of a transistor includes at least the following steps. An insulating layer is provided. A source/drain material layer is formed on the insulating layer to cover top surface and sidewalls of the insulating layer. A portion of the source/drain material layer is removed until the insulating layer is exposed, so as to form a source region and a drain region respectively on two opposite sidewalls of the insulating layer. A channel layer is deposited on the insulating layer, the source region, and the drain region. A ferroelectric layer is formed over the channel layer through a non-plasma deposition process. A gate electrode is formed on the ferroelectric layer. The gate electrode, the ferroelectric layer, and the channel layer are patterned to expose at least a portion of the insulating layer, at least a portion of the source region, and at least a portion of the drain region.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.