Patents by Inventor Cheng Yang

Cheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240092653
    Abstract: Niobium oxide particles which have a controlled crystal shape and exhibit excellent characteristics are provided. The niobium oxide particles include molybdenum. The niobium oxide particles preferably have a polyhedral, columnar or acicular shape. The MoO3 content (M1) measured by XRF analysis of the niobium oxide particles is preferably 0.1 to 40 mass % relative to the niobium oxide particles taken as 100 mass %. A method for producing the niobium oxide particles described above includes calcining a niobium compound in the presence of a molybdenum compound.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 21, 2024
    Inventors: Shaowei YANG, Jianjun YUAN, Masafumi UOTA, Mutsuko TANGE, Cheng LIU, Meng LI, Wei ZHAO, Jian GUO
  • Publication number: 20240096918
    Abstract: A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 21, 2024
    Inventors: Hao-Lin Yang, Tzu-Jui Wang, Wei-Cheng Hsu, Cheng-Jong Wang, Dun-Nian Yuang, Kuan-Chieh Huang
  • Publication number: 20240096943
    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Ta Yu, Hsiao-Chiu Hsu, Feng-Cheng Yang
  • Publication number: 20240096712
    Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Chieh-Fang Chen, Yen-Chung Ho, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240096677
    Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240098959
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240097010
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240092699
    Abstract: It relates to zirconia particles containing molybdenum and each having a polyhedron shape. The molybdenum is preferably unevenly distributed in surface layers of the zirconia particles. It also relates to a method for producing the zirconia particles. The method includes mixing a zirconium compound and a molybdenum compound to form a mixture and firing the mixture.
    Type: Application
    Filed: December 16, 2020
    Publication date: March 21, 2024
    Inventors: Shaowei YANG, Minoru TABUCHI, Jianjun YUAN, Cheng LIU, Meng LI, Wei ZHAO, Jian GUO
  • Publication number: 20240099086
    Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 21, 2024
    Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
  • Patent number: 11937426
    Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
  • Patent number: 11934585
    Abstract: A method for performing interactive operation upon a stereoscopic image and a stereoscopic image display system are provided. The stereoscopic image display system includes a stereoscopic display and a gesture sensor. In the method, the stereoscopic display displays the stereoscopic image, and the gesture sensor senses a gesture. A current gesture state is obtained. A previous state of the stereoscopic image and a previous gesture state are obtained. Stereo coordinate variations corresponding to the gesture can be calculated according to the current gesture state and the previous gesture state. New stereoscopic image data can be obtained according to the previous state of the stereoscopic image and the stereo coordinate variations corresponding to the gesture. The stereoscopic display is used to display a new stereoscopic image that is rendered from the new stereoscopic image data.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: March 19, 2024
    Assignee: LIXEL INC.
    Inventors: Arvin Lin, Yung-Cheng Cheng, Chun-Hsiang Yang
  • Patent number: 11933493
    Abstract: A tool includes a barrel, a guiding wire, and an electrically conductive member. The barrel is made of electrically conductive material. The guiding wire is disposed in the barrel. The barrel and the guiding wire are directly or indirectly connected to two opposite electrodes of a power source. The electrically conductive member is connected to an outer periphery of the guiding wire and is electrically connected to the guiding wire. The electrically conductive member is disposed between the barrel and the guiding wire and is spaced from the barrel. When the power source is activated, an electric arc is generated between the electrically conductive member and the barrel.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 19, 2024
    Assignee: PRO-IRODA INDUSTRIES, INC.
    Inventors: Wei Cheng Wu, Cheng Nan Yang
  • Patent number: 11936027
    Abstract: Embodiments of the present application provide a case for a battery, a battery, a power consumption device, and a method and device for producing a battery. The case includes: a thermal management component configured to adjust temperature of a battery cell accommodated in the case; a first wall provided with a through hole, the through hole being configured to communicate a gas inside and outside the case; and a condensing component attached to the thermal management component, the condensing component being configured to shield the through hole so as to condense a gas flowing into the inside of the case through the through hole. According to the technical solutions of the embodiments of the present application, the safety of the battery can be enhanced.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: March 19, 2024
    Assignee: JIANGSU CONTEMPORARY AMPEREX TECHNOLOGY LIMITED
    Inventors: Fenggang Zhao, Jiarong Hong, Xiaoteng Huang, Wenli Wang, Cheng Xue, Haiqi Yang, Langchao Hu
  • Publication number: 20240084135
    Abstract: A resin composition and uses thereof are provided. The resin composition includes: (A) an epoxy resin; (B) a bismaleimide resin; and (C) a first flame retardant having a structure of formula (I): Wherein Ar is a C3 to C18 heteroaryl or a C6 to C18 aryl; R1 is H or a C1 to C18 alkyl; and R2 and R3 are independently H, a C1 to C18 alkyl, a C3 to C18 heteroaryl, or a C6 to C18 aryl.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 14, 2024
    Inventors: Tsung-Hsien LIN, Shur-Fen LIU, Pin CHIEN, Kai-Cheng YANG
  • Publication number: 20240087932
    Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung TSAI, Ping-Cheng KO, Fang-yu LIU, Jhih-Yuan YANG
  • Publication number: 20240084455
    Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.
    Type: Application
    Filed: February 8, 2023
    Publication date: March 14, 2024
    Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Publication number: 20240087988
    Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Publication number: 20240082995
    Abstract: A hand tool (100,200) may include a head portion (110,210) configured to interface with a fastener, a shaft (120,220) and a grip portion at which an operator is enabled to hold the hand tool during operation, and a flexible interface (130,230) configured to operably couple the shaft and the head portion in a locked state and an unlocked state. The flexible interface is also configured to enable the head portion to pivot relative to the shaft about a pivot axis that extends substantially perpendicular to a direction of extension of the shaft. In the unlocked state, an angle of the head portion may be pivotable relative to the pivot axis. In the locked state, the angle of the head portion may be fixed. The flexible interface may include a locking assembly (150) including an actuator (152, 250, 250?) having a locked position defining the locked state and an unlocked position defining the unlocked state.
    Type: Application
    Filed: January 28, 2021
    Publication date: March 14, 2024
    Inventors: Minglin Shi, Cheng Yang, Yi-Hsiang Tseng, Tsung-Hsien Shen