Patents by Inventor Cheng-Yen Tsai
Cheng-Yen Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11322411Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.Type: GrantFiled: November 18, 2019Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
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Patent number: 11302582Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.Type: GrantFiled: November 18, 2019Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
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Patent number: 11282726Abstract: A method for measuring wafer bow value comprising the following steps is provided. Place a wafer on a wafer chuck apparatus. A gas inlet process is performed on gas inlet passageways of a passageway pair of the wafer chuck apparatus. A gas outlet process is performed on gas outlet passageways of a passageway pair of the wafer chuck apparatus. A leak rate of each channel pair is measured by the control unit when the wafer is placed on the wafer chuck apparatus and during the gas inlet process and gas outlet process are performed. A wafer bow value of the wafer on the wafer chuck apparatus is estimated by the leak rate of the passageway pair. A wafer chuck apparatus is provided. A semiconductor process flow is provided.Type: GrantFiled: July 23, 2019Date of Patent: March 22, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Cheng-Yen Tsai, Wei-Sheng Chen
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Publication number: 20210367076Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11121041Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.Type: GrantFiled: November 15, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
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Patent number: 11094828Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: June 22, 2020Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20210134799Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.Type: ApplicationFiled: December 14, 2020Publication date: May 6, 2021Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
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Publication number: 20210070615Abstract: This present invention provides a microporous carbon nanospheres, method for synthesizing and activating thereof, the method comprising: adding and mixing well deionized water, absolute ethanol, triblock copolymer, ammonia solution, resorcinol and formaldehyde solution; separating solid and liquid of the mixture solution, then drying the separated solid substrate to have a dried solid substrate; sintering the dried solid substrate surrounding by nitrogen twice and collecting microporous carbon nanospheres after cooling down. Further sintering to activate these microporous carbon nanospheres surrounding by carbon dioxide, and collecting activated microporous carbon nanospheres after cooling down. Microporous carbon nanospheres and activated microporous carbon nanospheres synthesized by this present invention have spherical structure, small size and high the specific surface area, and the process is simplified, cost-effective and environment-friendly.Type: ApplicationFiled: September 30, 2019Publication date: March 11, 2021Inventors: Yuan-Yao LI, Cheng-Yen Tsai, Li-Ming Chiang
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Publication number: 20210067546Abstract: A method for preventing denial of service attacks which are distributed attacks is applied in a target service provider server, a platform server, and a botnet service provider server. The target service provider server determines a first SDN controller according to an attack protection request, and issues a first flow rule. The target service provider server directs data flow of a network equipment to a first cleaning center and controls the first cleaning center to identify the attacking or malicious element in the data flow according to the first flow rule. The platform server receives the attacking element in the data flow sent by the target service provider server, and regards the same as malicious traffic. The platform server generates an attack report, and sends the attack report to the botnet service provider server to notify the botnet service provider server to clean or filter out the malicious traffic.Type: ApplicationFiled: November 10, 2020Publication date: March 4, 2021Inventor: CHENG-YEN TSAI
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Patent number: 10923576Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.Type: GrantFiled: January 23, 2020Date of Patent: February 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee
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Patent number: 10880329Abstract: A method for preventing denial of service attacks which are distributed attacks is applied in a target service provider server, a platform server, and a botnet service provider server. The target service provider server determines a first SDN controller according to an attack protection request, and issues a first flow rule. The target service provider server directs data flow of a network equipment to a first cleaning center and controls the first cleaning center to identify the attacking or malicious element in the data flow according to the first flow rule. The platform server receives the attacking element in the data flow sent by the target service provider server, and regards the same as malicious traffic. The platform server generates an attack report, and sends the attack report to the botnet service provider server to notify the botnet service provider server to clean or filter out the malicious traffic.Type: GrantFiled: August 26, 2019Date of Patent: December 29, 2020Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.Inventor: Cheng-Yen Tsai
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Patent number: 10868013Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.Type: GrantFiled: December 16, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
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Patent number: 10854725Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function metal layer is performed, where the fluorine-based treatment removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the fluorine-based treatment, another metal layer is deposited over the treated work-function metal layer.Type: GrantFiled: October 23, 2017Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee
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Publication number: 20200321252Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20200294828Abstract: A method for measuring wafer bow value comprising the following steps is provided. Place a wafer on a wafer chuck apparatus. A gas inlet process is performed on gas inlet passageways of a passageway pair of the wafer chuck apparatus. A gas outlet process is performed on gas outlet passageways of a passageway pair of the wafer chuck apparatus. A leak rate of each channel pair is measured by the control unit when the wafer is placed on the wafer chuck apparatus and during the gas inlet process and gas outlet process are performed. A wafer bow value of the wafer on the wafer chuck apparatus is estimated by the leak rate of the passageway pair. A wafer chuck apparatus is provided. A semiconductor process flow is provided.Type: ApplicationFiled: July 23, 2019Publication date: September 17, 2020Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Cheng-Yen Tsai, Wei-Sheng Chen
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Patent number: 10692770Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: May 30, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20200195003Abstract: An organic semiconductor device, a driving device and a driving method are provided. The driving device is configured to drive a load. The driving device includes a short circuit protection circuit and a delay circuit. The short circuit protection circuit is configured to provide an enable signal. The delay circuit provides a delay time length according to the energy passing through the load, and determines a start time point of the short circuit protection circuit to provide the enable signal according to the delay time length.Type: ApplicationFiled: December 25, 2018Publication date: June 18, 2020Applicant: Industrial Technology Research InstituteInventors: Hsuan-Yu Lin, Cheng-Yen Tsai
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Patent number: 10666742Abstract: A network service allocating system for a software defined network (SDN) includes an SDN controller, a plurality of SDN switches, a cloud server, and a local server. The SDN controller includes modules for service managing and path managing. Each SDN switch can receive a packet from a client and send the packet to the SDN controller. The service managing module analyzes the packet to identify type of service required and allocates the network service to the cloud server or to the local server according to the type of service required. The path managing module plans an optimum transmission path and sends the path to the SDN controller. Thereby, the SDN switch can obtain the network service. An SDN controller and a network service allocating method are also provided.Type: GrantFiled: January 23, 2017Date of Patent: May 26, 2020Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.Inventors: Cheng-Yen Tsai, Yu-Chung Lin, Yen-Chen Lu
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Publication number: 20200161443Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.Type: ApplicationFiled: January 23, 2020Publication date: May 21, 2020Inventors: Hsin-Yi LEE, Cheng-Yen TSAI, Da-Yuan LEE
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Patent number: 10658488Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.Type: GrantFiled: May 14, 2018Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee