Patents by Inventor Cheng-Yen Tsai

Cheng-Yen Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200130218
    Abstract: A food processing machine includes a driving mechanism, a connecting unit connected with the driving mechanism, a linkage connected with the connecting unit, and a cutter unit connected with the linkage. The connecting unit includes a driving lever and a driven handle. The linkage includes a disk, a primary rotation shaft, and a plurality of secondary rotation shafts. The cutter unit includes a plurality of connecting members and a plurality of cutters. Each of the cutters is provided with a first hooked portion and a second hooked portion. The first hooked portion of each of the cutters is to hooked onto the second hooked portion of an adjacent cutter, such that the cutters are drawn mutually by each other, to provide a larger cutting force to cut the elongated food strip when the cutters are retracted inward.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 30, 2020
    Inventor: Cheng-Yen Tsai
  • Publication number: 20200119019
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Publication number: 20200091006
    Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 19, 2020
    Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
  • Publication number: 20200083108
    Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
  • Publication number: 20200083114
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 10510756
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10510621
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 10504789
    Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
  • Publication number: 20190371675
    Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
  • Publication number: 20190371674
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20190318967
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 10304835
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10297453
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • Patent number: 10170417
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
  • Publication number: 20180338365
    Abstract: A driving module for driving at least a light emitting element is provided. The driving module includes a driving interface and a multi-channel driver. The driving interface is electrically connected to the light emitting element, and the driving interface includes multiple electric channels, wherein the electrical channels are selectively to be in a floating state or a connecting state. The multi-channel driver is electrically connected to the driving interface and transmits a constant current signal to the driving interface, wherein the constant current signal enters the light emitting element through the electrical channels in the connecting state. And, the total current value output by the driving interface is positively correlated with the area of the light emitting element which is as load. Further, a driving method utilizing the driving module is also provided.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 22, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Hsuan-Yu Lin, Cheng-Yen Tsai
  • Patent number: 10117305
    Abstract: A driving system and a driving method for a planar organic electroluminescent device are provided. The light emitting device has multiple light emitting elements, each having a first electrode and a second electrode. The driving system includes a first circuit, a second circuit, a driving module, and a ground circuit. The first circuit is connected to and provides a constant voltage to the first electrode of each light emitting element. The second circuit is connected to the second electrode of each light emitting element. The driving module is respectively connected to the second electrode of each light emitting element through the second circuit. The ground circuit is connected to the driving module and connects each light emitting element to the ground. The first electrodes of the light emitting elements are connected to one another, and the light emitting elements are driven by a constant current output by the driving module.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 30, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Hsuan-Yu Lin, Cheng-Yen Tsai, Sue-Chen Liao
  • Publication number: 20180261678
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Inventors: Hsin-Yi LEE, Cheng-Yen TSAI, Da-Yuan LEE
  • Publication number: 20180261459
    Abstract: A system for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Application
    Filed: May 15, 2018
    Publication date: September 13, 2018
    Inventors: Cheng-Yen TSAI, Hsin-Yi LEE, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG, Ming-Hsing TSAI
  • Patent number: 10051712
    Abstract: A driving module, being electrically connected to a control module and for driving a light emitting device with at least one light emitting element, is provided. The driving module has a driving circuit, which receives a control signal from the control module and transmits a drive current signal and a test current signal to the at least one light emitting element, so as to drive the least one light emitting element. A value of the drive current signal is expressed as If. A value of the test current signal is expressed as It. A relationship between the value of the drive current signal and the value of the test current signal satisfies the following equation (1), (It/If)=0.1%˜35% . . . (1), the driving circuit generates a feedback signal based on a status of the least one light emitting element. A light source system having the driving module is provided.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 14, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Yen Tsai, Hsuan-Yu Lin, Sue-Chen Liao, Pang-Min Shih
  • Publication number: 20180218912
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin