Patents by Inventor Cheng-Yi Wu

Cheng-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190265277
    Abstract: A circuit board for testing and a method of operating the same are provided. A relay is installed on a body of a circuit board having a probe. At least one external conductive line is arranged between the probe and the relay. During high-frequency signal testing, a transmission route is to transmit high-frequency signals to a test machine by means of the external conductive line, but is not to transmit high-frequency signals to a test machine by means of the relay. Accordingly, the limitation of the bandwidth condition of the relay can be avoided.
    Type: Application
    Filed: October 9, 2018
    Publication date: August 29, 2019
    Inventors: Sheng-Yu Tseng, Cheng-Yi Wu
  • Publication number: 20190131134
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Hong-Ying LIN, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sean Lo, C.W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Publication number: 20190093220
    Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 28, 2019
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Publication number: 20190088692
    Abstract: An image sensor includes a substrate having a first region and a second region. The image sensor further includes a dielectric layer over the substrate. The image sensor further includes a conductive layer over the dielectric layer, wherein in the first region the conductive layer has a grid shape and in the second region a portion of the conductive layer is concave toward the substrate. The image sensor further includes a protective layer, wherein the protective layer is over the conductive layer in the first region, and over a top surface and along sidewalls of the conductive layer in the second region.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Cheng-Yi WU, Chun-Chih LIN, Jian-Shin TSAI, Min-Hui LIN, Wen-Shan CHANG, Yi-Ming LIN, Chao-Ching CHANG, C. H. CHEN, Chin-Szu LEE, Y. T. TSAI
  • Publication number: 20180350601
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10147609
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20180337203
    Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Cheng-Yi WU, Chun-Chih LIN, Jian-Shin TSAI, Min-Hui LIN, Wen-Shan CHANG, Yi-Ming LIN, Chao-Ching CHANG, C. H. CHEN, Chin-Szu LEE, Y. T. TSAI
  • Publication number: 20180337128
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Patent number: 10134790
    Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Wu, Chun-Chih Lin, Jian-Shin Tsai, Min-Hui Lin, Wen-Shan Chang, Yi-Ming Lin, Chao-Ching Chang, C. H. Chen, Chin-Szu Lee, Y. T. Tsai
  • Patent number: 10062656
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Wen-Jen Tsai, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Yi-Ming Lin, Min-Hui Lin
  • Patent number: 10050102
    Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Chang, Cheng-Yi Wu, Jian-Shin Tsai, Min-Hui Lin, Yi-Ming Lin, Chin-Szu Lee, Wen-Shan Chang, Yi-Hui Chen
  • Patent number: 10038000
    Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Jian-Shin Tsai, Kuo-Hsien Cheng, Min-Hui Lin, Wei-Li Chen, Chao-Ching Chang, Chung-Yu Hsieh, Chin-Szu Lee
  • Publication number: 20180175196
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: March 31, 2017
    Publication date: June 21, 2018
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20180096936
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20180047682
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 15, 2018
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Wen-Jen Tsai, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Yi-Ming Lin, Min-Hui Lin
  • Publication number: 20170358446
    Abstract: A wafer processing apparatus includes at least one pedestal, at least one ultraviolet (UV) light source, and a window. The pedestal is configured to support a wafer. The UV light source is configured to generate UV radiation to the wafer. The window is present between the pedestal and the UV light source. The UV radiation is capable of passing through the window, and the window is a convex lens, a concave lens, or combinations thereof.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Cheng-Yi WU, Tzu-Shin Chen, Che-Kang Liu, Chi-Shun Wang, Chin-Szu LEE, Chia-Chun HUNG, Li-Hsuan CHU
  • Publication number: 20170250211
    Abstract: Semiconductor image sensor devices and manufacturing method of the same are disclosed. The semiconductor image sensor device includes a substrate, a first pixel and a second pixel, and an isolation structure. The first pixel and second pixel are disposed in the substrate, wherein the first and second pixels are neighboring pixels. The isolation structure is disposed in the substrate and between the first and second pixels, wherein the isolation structure includes a dielectric layer, and the dielectric layer includes silicon oxycarbonitride (SiOCN).
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20170207298
    Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Chao-Ching Chang, Cheng-Yi Wu, Jian-Shin Tsai, Min-Hui Lin, Yi-Ming Lin, Chin-Szu Lee, Wen-Shan Chang, Yi-Hui Chen
  • Patent number: 9704067
    Abstract: A method for automatically generating an image description includes following steps of: obtaining a first image data; analyzing a text file corresponding to the first image data; calculating occurrences and distribution ratios of terms, each of which contains a target word, from the text file, so as to obtain a plurality of the terms having the distribution ratios greater than a threshold; comparing the distribution ratios of the terms so as to find out at least one key term; finding out one of a plurality of lexical chains containing the key term with a greatest distribution ratio so as to generate a narrative language chain; and setting the narrative language chain as a description of the first image data. A system for automatically generating an image description and a non-volatile computer-readable storage media are also disclosed.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 11, 2017
    Assignee: National Yunlin University of Science and Technology
    Inventors: Chuen-Min Huang, Cheng-Yi Wu, Po-Hung Chen
  • Publication number: 20170084620
    Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Cheng-Yi WU, Jian-Shin TSAI, Kuo-Hsien CHENG, Min-Hui LIN, Wei-Li CHEN, Chao-Ching CHANG, Chung-Yu HSIEH, Chin-Szu LEE