Patents by Inventor Cheng Yi

Cheng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220247154
    Abstract: An edge emitting laser (EEL) device includes a substrate, an n-type buffer layer, a first n-type cladding layer, a grating layer, a spacer layer, a lower confinement unit, an active layer, an upper confinement unit, a p-type cladding layer, a tunnel junction layer and a second n-type cladding layer sequentially arranged from bottom to top. The tunnel junction layer can stop an etching process from continuing to form the second n-type cladding layer into a predetermined ridge structure and converting a part of the p-type cladding layer into the n-type cladding layer to reduce series resistance of the EEL device. Therefore, the optical field and active layer tend to be coupled at the middle of the active layer, the lower half of the active layer can be utilized effectively, and the optical field is near to the grating layer to achieve better optical field/grating coupling efficiency and lower threshold current.
    Type: Application
    Filed: January 6, 2022
    Publication date: August 4, 2022
    Inventors: CHENG-YI OU, CHIH-YUAN LIN, CHENG-HSIAO CHI
  • Patent number: 11404586
    Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
  • Publication number: 20220234084
    Abstract: A cleaning device includes a supporting mechanism, a clamping mechanism arranged on the supporting mechanism and used to clamp a spray head, a heating mechanism, an adjusting mechanism, and a cleaning mechanism. The heating mechanism, the adjusting mechanism, and the cleaning mechanism are arranged on the supporting mechanism. The heating mechanism is used to heat the spray head clamped by the clamping mechanism. The cleaning mechanism is used to inject cleaning liquid into the spray head, dredge the spray head, and detect the spray head. The adjusting mechanism is used to rotate and adjust a position of the cleaning mechanism to complete different tasks on the spray head.
    Type: Application
    Filed: March 4, 2021
    Publication date: July 28, 2022
    Inventor: JIAN-CHENG YI
  • Publication number: 20220238523
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
  • Publication number: 20220225512
    Abstract: An embedded circuit board made without gas bubbles or significant internal gaps according to a manufacturing method which is here disclosed comprises an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces, a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: CHENG-YI YANG, HAO-WEN ZHONG, BIAO LI, MING-JAAN HO, NING HOU
  • Publication number: 20220223218
    Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.
    Type: Application
    Filed: June 24, 2021
    Publication date: July 14, 2022
    Inventors: Chien-Hao HUANG, Cheng-Yi WU, Katherine H. CHIANG, Chung-Te LIN
  • Publication number: 20220224082
    Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a substrate, a first mirror layer, an active layer, an oxide layer, a second mirror layer, a tunnel junction layer and a third mirror layer sequentially stacked with one another. The first mirror layer and the third mirror layer are N-type distributed Bragg reflectors (N-DBR), and the second mirror layer is P-type distributed Bragg reflector (P-DBR). The tunnel junction layer is provided for the VCSEL device to convert a part of the P-DBR into N-DBR to reduce the series resistance of the VCSEL device, and the tunnel junction layer is not used as current-limiting apertures. This disclosure further discloses a VCSEL device manufacturing method with the in-situ and one-time epitaxy features to avoid the risk of process variation caused by moving the device into and out from an epitaxial cavity.
    Type: Application
    Filed: December 28, 2021
    Publication date: July 14, 2022
    Inventors: CHIH-YUAN LIN, CHENG-YI OU, TE-LIEH PAN, CHENG-HSIAO CHI
  • Publication number: 20220224080
    Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a substrate, a first mirror layer, a tunnel junction layer, a second mirror layer, an active layer, an oxide layer and a third mirror layer sequentially stacked with one another. The first mirror layer and the third mirror layer are N-type distributed Bragg reflectors (N-DBR), and the second mirror layer is P-type distributed Bragg reflector (P-DBR). The tunnel junction layer is provided for the VCSEL device to convert a part of the P-DBR into N-DBR to reduce the series resistance of the VCSEL device, and the tunnel junction layer is not used as current-limiting apertures. This disclosure further discloses a VCSEL device manufacturing method with the in-situ and one-time epitaxy features to avoid the risk of process variation caused by moving the device into and out from an epitaxial cavity.
    Type: Application
    Filed: December 22, 2021
    Publication date: July 14, 2022
    Inventors: CHENG-YI OU, CHIH-YUAN LIN, TE-LIEH PAN, CHENG-HSIAO CHI
  • Publication number: 20220223528
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20220220062
    Abstract: The present invention is directed to methods for the asymmetric synthesis of esketamine. The present invention is further directed to key intermediates in the asymmetric esketamine synthesis. In one embodiment, the invention is an asymmetric synthesis of esketamine comprising the conversion of (S)-2?-chloro-2-methoxy-3,4,5,6-5 tetrahydro-[1,1?-biphenyl]-3-yl carbamate to (S)-2?-chloro-1-isocyanato-6-methoxy-1,2,3,4-tetrahydro-1,1?-biphenyl.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 14, 2022
    Inventor: Cheng Yi CHEN
  • Publication number: 20220216301
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20220216040
    Abstract: A method and apparatus for dosage measurement and monitoring in an ion implantation system is disclosed. In one embodiment, a transferring system, includes: a vacuum chamber, wherein the vacuum chamber is coupled to a processing chamber; a shaft coupled to a ball screw, wherein the ball screw and the shaft are configured in the vacuum chamber; and a vacuum rotary feedthrough, wherein the vacuum rotary feedthrough comprises a magnetic fluid seal so as to provide a high vacuum sealing, and wherein the vacuum rotary feedthrough is configured through a first end of the vacuum chamber and coupled to the ball screw so as to provide a rotary motion on the ball screw.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Tsung-Min LIN, Fang-Chi Chien, Cheng-Yi Huang, Chao-Po Lu
  • Publication number: 20220208986
    Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Inventors: Chun Hsiung TSAI, Cheng-Yi PENG, Yin-Pin WANG, Kuo-Feng YU, Da-Wen LIN, Jian-Hao CHEN, Shahaji B. MORE
  • Publication number: 20220208317
    Abstract: An image content extraction method and an image content extraction device are disclosed. The method includes the following. An image file is obtained; the image file is analyzed to obtain distribution information of at least one grid in an image frame corresponding to the image file; template information is determined according to the distribution information of the at least one grid; text information is extracted from the image file according to the template information; and integration information related to a medical record of a user is generated according to the text information.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Yi Yang, Cheng-Liang Lin, Hsing-Chen Lin
  • Publication number: 20220204516
    Abstract: Disclosed is a process for the preparation of certain intermediates, e.g. a process R for preparing a compound of formula (I) wherein, R1, R2 and X1 are as defined in the description, and which intermediate and processes are useful in the preparation of a BTK inhibitor, such as ibrutinib.
    Type: Application
    Filed: May 20, 2020
    Publication date: June 30, 2022
    Inventors: Philip James PYE, Andras HORVATH, Cheng Yi CHEN, Yuanyuan Yuan, Jinxiong SU, Shuo WANG, Simon Albert WAGSCHAL
  • Patent number: 11373910
    Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0<a, 0<b, 0.01?(a+b)?0.1, 0.01?y?0.1, and M2 is P or As.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Cheng-Yi Peng, Ziwei Fang, I-Ming Chang, Akira Mineji, Yu-Ming Lin, Meng-Hsuan Hsiao
  • Publication number: 20220192507
    Abstract: A method for dynamic physiological characteristic region capturing includes: detecting a human body and generate thermal images with continuous time-sequence data; detecting the thermal images and locate a skeleton from one thermal images; based on the skeleton to capture a nose and a human face, the human face is set as an ROI is further divided into image blocks; relating the image blocks to the thermal images; based on variation of temperature information in continuous time-sequence data for the image blocks to divide the image blocks into the first and the second frequency variation blocks; and, analyzing the temperature information in the continuous time-sequence data to the first and the second frequency variation blocks to obtain different physiological information of the human body. In addition, a system for the same is also provided.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Inventors: Hsing-Chen Lin, Cheng-Yi Yang, Zhong-Wei Liao, Cheng-Lii Chang
  • Patent number: 11367632
    Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Wen Wu, Chun-Ta Chen, Chin-Shen Hsieh, Cheng-Yi Huang
  • Publication number: 20220183573
    Abstract: A non-invasive method for measuring the motion characteristics of myocardial tissue includes transmitting a plurality of generated synchronous orthogonal, phase controllable and adjustable alternating currents with different frequencies to an organism so as to generate a plurality of synchronous periodic AC voltage signals with different frequencies; receiving the periodic AC voltage signals modulated by changes in the organism's heart tissue to obtain the organism's frequency responses; calculating resistances and capacitances of the heart tissue according to the frequency responses; estimating motion characteristics of myocardial tissue according to the resistances and the capacitances. By means of introducing the average longitudinal length of the myocardial cells, and calculating changes in the average longitudinal length of the myocardial cells according to the capacitances, the overall longitudinal elasticity of the heart is described.
    Type: Application
    Filed: April 18, 2019
    Publication date: June 16, 2022
    Inventors: Ling WANG, Cheng YI, Bixia HE, Peng XIE
  • Patent number: 11359945
    Abstract: An inspection device for subway tunnel based on three-dimensional laser scanning includes a three-dimensional laser scanner, an adaptive structure of a track trolley, a power control module for the track trolley, a photoelectric sensor and a body of the track trolley. The power control module is arranged on the body. A support rod is vertically arranged on the power control module, and the three-dimensional laser scanner is mounted at a top of the support rod. The adaptive structure is symmetrically arranged at two sides of the body of the track trolley, and the photoelectric sensor is arranged in the body of the track trolley. The inspection device is designed to be modular, which is convenient to carry and repair, and easy to mount. In addition, the inspection device has low labor cost due to less manual intervention, and the inspection efficiency can be improved.
    Type: Grant
    Filed: February 7, 2021
    Date of Patent: June 14, 2022
    Assignee: Nanjing University of Aeronautics and Astronautics
    Inventors: Jun Wang, Dawei Li, Yuxiang Wu, Cheng Yi, Xu Xu