Abstract: The present invention provides a photodiode, which includes: a light absorption substrate, a first electrode portion, a second electrode portion, an antireflection layer, and a distributed Bragg reflection layer. The antireflection layer is arranged to receive light to get into the light absorption substrate. The antireflection layer is arranged to receive light to get into the light absorption substrate, and the distributed Bragg reflection layer is arranged to reflect light transmitting through the light absorption substrate to exit from the light absorption substrate back to the light absorption substrate, in order to enhance the photocurrent and the spectrum sensitivity of the photodiode.

Abstract: A portable electronic device and a plate antenna module thereof are provided. The plate antenna module includes an antenna carrying structure, an inner surrounding radiation structure, a first inner feeding structure, an outer surrounding radiation structure, and a first outer feeding structure. The first inner feeding structure is surrounded by the inner surrounding radiation structure. The inner surrounding radiation structure is surrounded by the outer surrounding radiation structure. The inner surrounding radiation structure and the outer surrounding radiation structure are respectively disposed on two different planes of the antenna carrying structure.

Abstract: A method for automatically processing a structure-reinforcing member of an aircraft, including: (S1) acquiring, by a handheld laser scanner, data of an area to be reinforced of the aircraft; (S2) controlling a robotic arm to automatically grab the reinforcing member for automatic scanning; (S3) setting a cutting path in a computer aided design (CAD) digital model followed by registration with real data to obtain an actual cutting path, and cutting the reinforcing member; (S4) controlling the robotic arm to guide a cut reinforcing member to a scanning area for automatic scanning; and (S5) subjecting point cloud data of the cut reinforcing member and the area to be reinforced to virtual assembly and calculating a machining allowance to determine whether an accuracy requirement is met; if yes, ending a task; otherwise, grinding the reinforcing member automatically, and repeating steps (S4)-(S5).

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: The present invention relates to adenine which is useful to activate AMP-activated protein kinase (AMPK) and the use of adenine in the prevention or treatment of conditions or disease and thereby prevent or treat conditions or diseases which can be ameliorated by AMPK in a mammal.

Abstract: An optical imaging lens assembly, which is applied for an endoscopic optical device, from an object side to an image side aligned in order includes a first lens element, a second lens element and a third lens element. The first lens element has negative refracting power, and further has a first convex object-side surface and a first image-side surface. The second lens element has positive refracting power, and further has a second convex object-side surface and a second concave image-side surface. The third lens element has positive refracting power, and further has a third convex image-side surface and a third object-side surface.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: Provided is an electronic device for a temporal synchronization, which determines a set of parameters associated with each imaging device of a plurality of imaging devices. The set of parameters include frame rate of each imaging device. The electronic device generates a synchronization signal that includes a preamble pulse of a first time duration set based on the frame rate and a sequence of alternating ON and OFF pulses. Each pulse of the sequence of alternating ON and OFF pulses is of a second time duration set based on the set of parameters. Based on the synchronization signal, lighting devices may be controlled to generate a pattern of alternating light pulses that is captured by each imaging device. The electronic device further acquires a plurality of images that includes information about the pattern of alternating light pulses. The electronic device further synchronizes the plurality of images, based on the information.

Abstract: Examples of electronic devices and connectors for providing a secure connection are described herein. In an example, an electronic device may securely hold an external device, upon engagement of a connector of the external device in a corresponding port of the electronic device.

Abstract: Throughput is preserved in a distributed system while maintaining concurrency by pushing a commit wait period to client commit paths and to future readers. As opposed to servers performing commit waits, the servers assign timestamps, which are used to ensure that causality is preserved. When a server executes a transaction that writes data to a distributed database, the server acquires a user-level lock, and assigns the transaction a timestamp equal to a current time plus an interval corresponding to bounds of uncertainty of clocks in the distributed system. After assigning the timestamp, the server releases the user-level lock. Any client devices, before performing a read of the written data, must wait until the assigned timestamp is in the past.

Abstract: In an example, an electronic device may include a housing and a first acoustic device pivotally disposed in the housing. The first acoustic device may move between a first position within the housing and a second position outside the housing. The first acoustic device may direct an acoustic signal in a direction. Further, the electronic device may include a camera to capture an image of an area in front of the electronic device. Furthermore, the electronic device may include a processor operatively coupled to the camera and the first acoustic device. The processor may determine a location of a facial feature of an operator using the captured image. Further, the processor may control an angle of rotation of the first acoustic device relative to the housing based on the location of the facial feature to modify the direction of the acoustic signal.

Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.

Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.

Abstract: An air handling unit control system is applied to an air handling unit having a plurality of hardware devices. The air handling unit control system includes at least one expansion module and a main controller. The at least one expansion module is configured to be electrically connected to at least one expanded hardware device. The main controller is electrically connected to the expansion module to control the expanded hardware device. The main controller provides a setting interface according to the hardware devices and the expanded hardware device. The setting interface includes a plurality of setting items. When at least one of the setting items is triggered, the main controller executes a corresponding setting procedure according to the triggered setting item to set up the hardware devices and the expanded hardware device.

Abstract: A movable device and a block-type millimeter wave array antenna module thereof are provided. The block-type millimeter wave array antenna module includes an antenna carrying substrate, an antenna signal transmitting group, an antenna signal receiving group, and a dummy antenna group. The antenna carrying substrate includes a plurality of block-shaped carrier bodies that are divided into a plurality of first, second, third, and fourth antenna carrier blocks. The antenna signal transmitting group includes a plurality of signal transmitting antenna structures respectively carried by the first antenna carrier blocks. The antenna signal receiving group includes a plurality of signal receiving antenna structures respectively carried by the second antenna carrier blocks. The dummy antenna group includes a plurality of first dummy antenna structures respectively carried by the third antenna carrier blocks, and a plurality of second dummy antenna structures respectively carried by the fourth antenna carrier blocks.

Abstract: A detection method for rogue access points is disclosed. Timestamps of beacon packets of each access point (AP) in multiple wireless AP are collected. Clock skews of each of the APs are calculated based on the collected timestamps. Clock skew models of each of the APs are established according to the clock skews of each of the APs. It is determined whether a rogue AP is detected. A plurality of legal APs adjacent to the rogue AP are selected if the rogue AP is detected. Received signal strength indicator (RSSI) values relative to the rogue AP are collected via the selected legal APs. The rogue AP is localized according to the collected RSSI values.

Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Abstract: A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.