Patents by Inventor Cheng Yi

Cheng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES
    Publication number: 20220384613
    Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second SID regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Lid.
    Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
  • Semiconductor test device and manufacturing method thereof
    Patent number: 11513145
    Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Ming-Shiang Lin, Chih-Sheng Chang, Carlos H. Diaz
  • PORTABLE ELECTRONIC DEVICE AND PLATE ANTENNA MODULE THEREOF
    Publication number: 20220376399
    Abstract: A portable electronic device and a plate antenna module thereof are provided. The plate antenna module includes an antenna carrying structure, an inner surrounding radiation structure, a first inner feeding structure, an outer surrounding radiation structure, and a first outer feeding structure. The first inner feeding structure is surrounded by the inner surrounding radiation structure. The inner surrounding radiation structure is surrounded by the outer surrounding radiation structure and separate from the outer surrounding radiation structure. The first outer feeding structure corresponds to the first inner feeding structure.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 24, 2022
    Inventors: Ta-Fu Cheng, Cheng-Yi Wang, Wei-Lin Liu, Shou-Jen Li
  • Method of forming semiconductor device package
    Patent number: 11508710
    Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
  • NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220367565
    Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
    Type: Application
    Filed: June 11, 2021
    Publication date: November 17, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Yi Lin, Tang Chun Weng, Chia-Chang Hsu, Yung Shen Chen, Chia-Hung Lin
  • PERMEANCE MAGNETIC ASSEMBLY
    Publication number: 20220367160
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MEMORY REPAIR
    Publication number: 20220366996
    Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Katherine H. CHIANG, Chien-Hao HUANG, Cheng-Yi WU, Chung-Te LIN
  • Method for activating AMPK and the use of adenine
    Patent number: 11497748
    Abstract: The present invention relates to adenine which is useful to activate AMP-activated protein kinase (AMPK) and the use of adenine in the prevention or treatment of conditions or disease and thereby prevent or treat conditions or diseases which can be ameliorated by AMPK in a mammal.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 15, 2022
    Assignee: Energenesis Biomedical Co., Ltd.
    Inventors: Han-Min Chen, Cheng-Yi Kuo, Chun-Fang Huang, Jiun-Tsai Lin
  • Multi-user downlink orthogonal frequency-division multiple access configuration method
    Patent number: 11502795
    Abstract: A multi-user downlink orthogonal frequency-division multiple access (OFDMA) configuration method includes: assigning contiguous resource units (RUs) included in a channel to a plurality of stations, respectively; and assigning, by an access point (AP), one modulation and coding scheme (MCS) to each of the plurality of stations. Data rates of modulation and coding schemes that are assigned to first stations and associated with contiguous first RUs assigned to the first stations are monotonic, where the first stations are included in the plurality of stations.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: November 15, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hsien Chang, Ying-You Lin, Kuan-I Li, Ping-Chen Lin, Po-Hsun Wei, Cheng-Yi Chang
  • Augmented reality device
    Patent number: 11500214
    Abstract: An augmented reality (AR) device includes a main body, a support element, and a lens module. The main body includes a base, a projector, and a first pivot portion. The projector is pivoted to the base by using the first pivot portion, so that the projector is capable of rotating relative to the base by using the first pivot portion as a first rotation axis. The support element is pivoted to a first end portion of the base and is configured to wear on a head of a user. The lens module is pivoted to a second end portion of the base and the second end portion is opposite to the first end portion. The lens module is capable of rotating relative to the base and being overlapped under the base. Through a rotatable and foldable accommodation structure, the augmented reality device is easier to be carried and accommodated.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: November 15, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chih-Cheng Chung, Hsiao-Cheng Chen, Cheng-Yi Lee
  • SEALING ARTICLE COMPRISING METAL COATING, METHOD OF MAKING AND METHOD OF USING THE SAME
    Publication number: 20220356571
    Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Peng-Cheng HONG, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • RESIN COMPOSITION, ENCAPSULATION STRUCTURE, AND METHOD FOR MANUFACTURING RESIN COMPOSITION
    Publication number: 20220356342
    Abstract: A resin composition is provided, which includes a first polymer and a second polymer. The first polymer is formed by a reaction of an epoxy resin modified with a first elastic molecular segment and an epoxy resin curing agent. The second polymer is formed by a polymerization of an acrylate modified with a second elastic molecular segment.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 10, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Yi LIN, Shih-Ming CHEN
  • SPACE FILLING DEVICE FOR WET BENCH
    Publication number: 20220359236
    Abstract: The disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. The space filling device has an overall density that is higher than the chemicals used to purge the wet bench. As such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. As a result, less purging chemicals are used to fill and bath the wet bench.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Yen-Ji CHEN, Chih-Shen YANG, Cheng-Yi HUANG
  • Power supply with duty cycle limiting circuit, duty cycle limiting circuit, and method of operating the same
    Patent number: 11496048
    Abstract: A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 8, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ming-Wei Chou, Sheng-Jian Chen, Chia-Chang Hsu, Cheng-Yi Lo
  • Memory repair using optimized redundancy utilization
    Patent number: 11495314
    Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hao Huang, Cheng-Yi Wu, Katherine H. Chiang, Chung-Te Lin
  • TRANSISTOR INCLUDING A HYDROGEN-DIFFUSION BARRIER AND METHODS FOR FORMING THE SAME
    Publication number: 20220352333
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Application
    Filed: November 11, 2021
    Publication date: November 3, 2022
    Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
  • DETECT MECHANISM USING ELECTRICAL CONNECTIONS
    Publication number: 20220350376
    Abstract: In some examples a computing device can comprise a back plate and an electrical connection. The electrical connection is not in contact with a detect mechanism if a first voltage is generated; and the detect mechanism is in contact with the electrical connection if a second voltage is generated.
    Type: Application
    Filed: October 18, 2019
    Publication date: November 3, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Cheng-Yi Yang, Szu-Tao Tong, Hai-Lung Hung, Chia Ching Lu
  • SPUTTERING TARGET ASSEMBLY TO PREVENT OVERETCH OF BACKING PLATE AND METHODS OF USING THE SAME
    Publication number: 20220351953
    Abstract: A sputtering target assembly, sputtering apparatus, and method, the target assembly including a backing plate having an aperture formed therein; and a target bonded to a front surface of the backing plate. The aperture is disposed on the backing plate such that a first end of the aperture is sealed by a portion of the target that is predicted by a sputtering target erosion profile to have the highest etching rate during a corresponding sputtering process.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 3, 2022
    Inventors: Chen-Fang CHUNG, Wen-Cheng CHENG, Po Wen YANG, Ming-Jie HE, Yan-Zi LU, Cheng-Yi TENG
  • Compositions and methods for maintaining cell viability
    Patent number: 11485953
    Abstract: The present disclosure provides for a cell stabilizing medium which comprises gelatin. The cell stabilizing medium help maintain cell viability, e.g., after thawing of a biological material post-cryopreservation.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 1, 2022
    Assignee: TRANSWELL BIOTECH CO., LTD.
    Inventors: Ya-Hsuan Chang, Cheng-Yi Lin, Chih-Yuan Chao
  • Frequency and spatial domain image processing method for image marking and mark detection, apparatus, and storage medium
    Patent number: 11489984
    Abstract: This application relates to an image processing method and apparatus, a storage medium, and a computer device. The method includes: obtaining a frequency domain mark image, the frequency domain mark image being obtained by performing frequency domain transformation on a spatial domain mark image; obtaining a transparency parameter configured corresponding to the frequency domain mark image; obtaining target page data; and performing layer superimposition rendering of the frequency domain mark image and the target page data according to the transparency parameter. The solution provided in this application can effectively protect target page data.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 1, 2022
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Cheng Yi, Cheng Luo, Bin Li