Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

Abstract: The present invention provides a compound of Formula (I) or a pharmaceutically acceptable salt thereof wherein R1, R2, R3, A1, A2, A3, A4, L, B1, B2, B3 and B4 are as defined herein. The compounds of Formula I have been found to act as glucagon antagonists or inverse agonists. Consequently, the compounds of Formula I and the pharmaceutical compositions thereof are useful for the treatment of diseases, disorders, or conditions mediated by glucagon.

Abstract: The present invention provides a compound of Formula (I) or a pharmaceutically acceptable salt thereof wherein R1, R2, R3, A1, A2, A3, A4, L, B1, B2, B3 and B4 are as defined herein. The compounds of Formula I have been found to act as glucagon antagonists or inverse agonists. Consequently, the compounds of Formula I and the pharmaceutical compositions thereof are useful for the treatment of diseases, disorders, or conditions mediated by glucagon.

Abstract: The present invention provides a compound of Formula (I) or a pharmaceutically acceptable salt thereof wherein R1, R2, R3, A1, A2, A3, A4, L, B1, B2, B3 and B4 are as defined herein. The compounds of Formula I have been found to act as glucagon antagonists or inverse agonists. Consequently, the compounds of Formula I and the pharmaceutical compositions thereof are useful for the treatment of diseases, disorders, or conditions mediated by glucagon.

Abstract: The present invention provides a compound of Formula (I) or a pharmaceutically acceptable salt thereof wherein R1, R2, R3, A1, A2, A3, A4, L, B1, B2, B3 and B4 are as defined herein. The compounds of Formula I have been found to act as glucagon antagonists or inverse agonists. Consequently, the compounds of Formula I and the pharmaceutical compositions thereof are useful for the treatment of diseases, disorders, or conditions mediated by glucagon.

Abstract: A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.

Abstract: A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface.

Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

Abstract: This invention is applicable to a Virtual Private LAN service built using multiple point-to-point Ethernet services from a network operator, where the bridging and the transport/tunneling of Ethernet frames to a remote site are decoupled. The learning bridge function (including MAC address learning and flooding) is performed at customer equipment CE devices, while the tunneling is performed at provider edge PE nodes. The models described here for this VPN refer to hub redundancy, site-to-site SLA guarantees and address discovery in the case of hybrid connections.

Abstract: A system and method are provided for forwarding packets through a fully meshed communication network when the destination MAC address may not be known. Each network element maintains a mapping of MAC addresses and IP addresses, each MAC address having an associated IP address which indicates to where packets are to be forwarded. If a network element receives a packet but has not yet associated an IP address with the destination MAC address of the packet, then the network element forwards the packet along a tree. If a network element receives a packet and has associated an IP address with the destination MAC address, in other words has learned of the IP address for the MAC address, the network element sends the packet directly to the IP address unless a direct link to the IP address is not available. If a direct link is not available, the network element forwards the packet along the tree.

Abstract: A stackable semiconductor package includes first and second substrates, a semiconductor device, first wires, a supporting element, and a first molding compound. The semiconductor device is disposed on the first substrate. The second substrate is disposed above the semiconductor device, and the area of the second substrate is larger than that of the semiconductor device. The first wires electrically connect the first and second substrates. The supporting element is disposed between the first and second substrates, and supports the second substrate. Some pads of the second substrate are exposed outside the first molding compound. Therefore, the overhang portion of the second substrate will not shake or sway during wire bonding, and the area of the second substrate can be increased to have more devices thereon. Also, the thickness of the second substrate can be reduced, to reduce the overall thickness of the stackable semiconductor package.

Abstract: A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.

Abstract: A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface.

Abstract: A semiconductor package includes a carrier, at least one chip, an encapsulation, and a patterned conductive film. The carrier has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the carrier and electrically connected to the carrier. The encapsulation encapsulates the chip and at least a portion of the first surface of the carrier. The patterned conductive film is disposed on the encapsulation to electrically connect to the carrier. A manufacturing method of the semiconductor package is also disclosed.

Abstract: A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

Abstract: A manufacturing method of a package structure is provided. Firstly, a substrate having a surface is provided. Next, a chip is disposed on the surface of the substrate. Then, a packing material layer is formed on the surface of the substrate. Next, a this film is pasted on the packing material layer. Then the substrate and the packing material layer are thoroughly cut along a cutting line around the chip by a first cutting blade but the thin film is not cut thoroughly. Next, the substrate is thoroughly cut along at least a part of the cutting line by a second cutting blade but the packing material layer is not thoroughly cut such that a part of the packing material layer is exposed. The width of the second cutting blade is larger than the width of the first cutting blade.

Abstract: The present invention discloses a solution which delivers routing systems with less path setup latency and causes them to be less susceptible to network loading, by providing them the ability to setup diverse paths as a result of specifying network resources to exclude as part of a path setup. The invention proposes an extension to RSVP-TE in the form of a new RSVP-TE object, known as an Exclude Route Object, which will allow, in a path setup request, the specification of a set of abstract nodes and resources to be explicitly excluded from the path. Additionally, the invention introduces a second type of exclusion which is achieved through a modification to the existing Explicit Route Object (ERO) by allowing a node to specify, in a path setup request, the exclusion of certain abstract nodes and resources between a specific pair of abstract nodes within an Explicit Route Object.

Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.