Patents by Inventor Cheng-Yin Lee

Cheng-Yin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080023816
    Abstract: A semiconductor package mainly includes a carrier, a package having a first surface and a second surface, a chip and a plurality of bonding wires. The package is disposed on an upper surface of the carrier and electrically connected to the carrier by a plurality of conductive elements, the chip is disposed on the second surface of the package, a plurality of pads of the chip are corresponding to an opening of the carrier, and the bonding pads of the chip are electrically connected to a plurality of conductive pads of the carrier by the bonding wires to lower the height of the semiconductor package and increase the space for circuit layout.
    Type: Application
    Filed: May 3, 2007
    Publication date: January 31, 2008
    Inventors: Gwo-Liang Weng, Cheng-Yin Lee
  • Publication number: 20070278696
    Abstract: The present invention relates to a stackable semiconductor package including a first substrate, a chip, a low modules film, a second substrate, a plurality of first wires, and a first molding compound. The chip is disposed on the first substrate. The low modules film is disposed on the chip. The second substrate is disposed on the low modules film. The area of the low modules film is adjusted according to the area of the second substrate, so as to support the second substrate. The first wires electrically connect the first substrate and the second substrate. Some pads of the second substrate are exposed outside the first molding compound. Therefore, the overhang portion of the second substrate will not shake or sway during a wire bonding process, and the area of the second substrate can be increased to receive more devices disposed thereon. In addition, the thickness of the second substrate can be reduced, so as to reduce the overall thickness of the stackable semiconductor package.
    Type: Application
    Filed: December 12, 2006
    Publication date: December 6, 2007
    Inventors: Yung-Li Lu, Cheng-Yin Lee, Ying-Tsai Yeh
  • Publication number: 20070278640
    Abstract: The present invention relates to a stackable semiconductor package comprising a first substrate, a semiconductor device, a second substrate, a plurality of first wires, a supporting element, and a first molding compound. The semiconductor device is disposed on the first substrate. The second substrate is disposed above the semiconductor device, and the area of the second substrate is larger than that of the semiconductor device. The first wires electrically connect the first substrate and the second substrate. The supporting element is disposed between the first substrate and the second substrate, and is used to support the second substrate. Some pads of the second substrate are exposed outside the first molding compound. Therefore, the overhang portion of the second substrate will not shake or sway during a wire bonding process, and the area of the second substrate can be increased to receive more devices disposed thereon.
    Type: Application
    Filed: December 12, 2006
    Publication date: December 6, 2007
    Inventors: Gwo-Liang Weng, Yung-Li Lu, Cheng-Yin Lee
  • Publication number: 20070252284
    Abstract: The present invention relates to a stackable semiconductor package. The stackable semiconductor package includes a first substrate, a chip, a first molding compound, a second substrate, a plurality of first wires, and a second molding compound. The chip is disposed on the first substrate. The second substrate is disposed on the first molding compound. The area of the first molding compound is adjusted according to the area of the second substrate, so as to support the second substrate. The first wires electrically connect the first substrate and the second substrate. Some pads of the second substrate are exposed outside the second molding compound. Therefore, the second substrate will not shake or sway during a wire bonding process, and the area of the second substrate can be increased to receive more devices disposed thereon.
    Type: Application
    Filed: December 12, 2006
    Publication date: November 1, 2007
    Inventors: Po-Ching Su, Cheng-Yin Lee, Ying-Tsai Yeh, Gwo-Liang Weng
  • Publication number: 20070243704
    Abstract: The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
    Type: Application
    Filed: December 6, 2006
    Publication date: October 18, 2007
    Inventors: Wei-Chang Tai, Chi-Chih Chu, Meng-Jung Chuang, Cheng-Yin Lee, Yao-Ting Huang, Kuang-Lin Lo
  • Patent number: 7280543
    Abstract: A method of processing OAM messages by network elements in a communications network is described. Elements in the network are provided with configuration information respecting OAM messages together with connection signaling upon setting up a call through the network. Each network element interprets the OAM messages and derives therefrom configuration information for use in executing an OAM function.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: October 9, 2007
    Assignee: Alcatel Canada Inc.
    Inventors: Cheng-Yin Lee, Amr Elkady
  • Publication number: 20070224732
    Abstract: A manufacturing method of a package structure is provided. Firstly, a substrate having a surface is provided. Next, a chip is disposed on the surface of the substrate. Then, a packing material layer is formed on the surface of the substrate. Next, a thin film is pasted on the packing material layer. Then, the substrate and the packing material layer are thoroughly cut along a cutting line around the chip by a first cutting blade but the thin film is not cut thoroughly. Next, the substrate is thoroughly cut along at least a part of the cutting line by a second cutting blade but the packing material layer is not thoroughly cut such that a part of the packing material layer is exposed. The width of the second cutting blade is larger than the width of the first cutting blade.
    Type: Application
    Filed: December 13, 2006
    Publication date: September 27, 2007
    Inventors: Gwo-Liang Weng, Cheng-Yin Lee
  • Publication number: 20070132093
    Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.
    Type: Application
    Filed: May 25, 2006
    Publication date: June 14, 2007
    Inventors: Meng-Jung Chuang, Cheng-Yin Lee, Wei-Chang Tai, Chi-Chih Chu
  • Publication number: 20070090507
    Abstract: A multi-chip package structure includes a first substrate, a first chip, a sub-package, and a first molding compound. The first substrate has a first surface and a second surface. The first chip is attached to the first surface of the first substrate by flip-chip bonding so as to reduce a step of wire bonding and reduce the total height of the package structure. The sub-package includes a second substrate, a second chip, and a second molding compound. The second substrate has a first surface and a second surface. The second substrate is a flexible substrate and is directly connected to the first surface of the first substrate so as to reduce another step of wire bonding.
    Type: Application
    Filed: January 17, 2006
    Publication date: April 26, 2007
    Inventors: Chian-Chi Lin, Cheng-Yin Lee
  • Publication number: 20070090508
    Abstract: The present invention relates to a multi-chip package structure, which comprises a first substrate, a first chip, a sub-package structure, a plurality of first solder balls, and a first molding compound. The first substrate has a first surface and a second surface. The first chip is electrically connected to the first surface of the first substrate. The sub-package structure comprises a second substrate, a second chip, and a second molding compound. The first solder balls are disposed between the first substrate and the second substrate and are used for connecting the first surface of the first substrate and the second surface of the second substrate so as to omit a step of wire bonding.
    Type: Application
    Filed: September 14, 2006
    Publication date: April 26, 2007
    Inventors: Chian-Chi Lin, Cheng-Yin Lee
  • Publication number: 20070075441
    Abstract: A chip package structure including a chip, a carrier, a plurality of bonding wires and a molding compound is provided. The chip has an active surface, a back surface opposite to the active surface, a plurality of side surfaces, and a plurality of flash-preventing surfaces located between the active surface and the side surfaces. The carrier is connected to the back surface of the chip to carry the chip. The chip is electrically connected to the carrier via the bonding wires. The molding compound is disposed on the carrier and encapsulates the bonding wires, a portion of the active surface, the side surfaces, and at least a portion of the flash-preventing surfaces. The flash-preventing surfaces prevent excess molding compound from contaminating the active surface of the chip.
    Type: Application
    Filed: August 9, 2006
    Publication date: April 5, 2007
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yin Lee, Yung-Li Lu, Po-Ching Su
  • Publication number: 20070072341
    Abstract: The present invention relates to a die package and method for making the same. The method of the invention comprises the steps of: (a) providing a plate, having a first surface and a second surface; (b) forming a plurality of first dice on the plate, the first dice having a first surface and a second surface; (c) forming a plurality of bumps on the first surface of the first dice; and (d) cutting the plate to form a plurality of die modules, each module comprising a plate unit, a first die and a plurality of bumps, the first die disposed on a first surface of the plate unit, whereby the bumps could be easily mounted on the single die.
    Type: Application
    Filed: August 17, 2006
    Publication date: March 29, 2007
    Inventors: Wei-Chang Tai, Cheng-Yin Lee
  • Publication number: 20070058622
    Abstract: A system and method are provided for forwarding packets through a fully meshed communication network when the destination MAC address may not be known. Each network element maintains a mapping of MAC addresses and IP addresses, each MAC address having an associated IP address which indicates to where packets are to be forwarded. If a network element receives a packet but has not yet associated an IP address with the destination MAC address of the packet, then the network element forwards the packet along a tree. If a network element receives a packet and has associated an IP address with the destination MAC address, in other words has learned of the IP address for the MAC address, the network element sends the packet directly to the IP address unless a direct link to the IP address is not available. If a direct link is not available, the network element forwards the packet along the tree.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Applicant: ALCATEL
    Inventor: Cheng-Yin Lee
  • Publication number: 20070052082
    Abstract: A multi-chip package structure including a carrier, a first chip having an active surface and a rear surface, multiple bumps, a second chip, multiple first bonding wires, a package unit disposed above the first chip, a spacer disposed between the package unit and the first chip, multiple second bonding wires, and an encapsulant is provided. The bumps are disposed between the active surface and the carrier to electrically connect the first chip and the carrier. The second chip is disposed on the rear surface of the first chip. The first bonding wires electrically connect the second chip and the carrier. The second bonding wires electrically connect the package unit and the carrier. The encapsulant is disposed on the carrier to encapsulate the first chip, the second chip, at least a portion of the package unit, the bumps, the spacer, the first bonding wires and the second bonding wires.
    Type: Application
    Filed: January 12, 2006
    Publication date: March 8, 2007
    Inventors: Cheng-Yin Lee, Chih-Ming Chung, Wen-Pin Huang
  • Patent number: 7187070
    Abstract: A Stackable package module comprises a plurality of semiconductor devices in stack. One of the semiconductor devices includes a chip with an active surface and a corresponding back surface, a plurality of solder bumps and a plurality of stud bumps. The solder bumps are formed on the active surface. The stud bumps are formed on the back surface. Each stud bump has a bump body and a protruding trail by wire-bonding and cutting. Bumps of another package are bonded on the stub bumps for replacing known intermediate substrate in conventional stacked package module.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: March 6, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Chih Chu, Cheng-Yin Lee, Gwo-Liang Weng, Shih-Chang Lee
  • Patent number: 7122757
    Abstract: A contact sensor package has a substrate, a film, a sealant and a plurality of contact sensors disposed on the substrate. The contact sensors are disposed within the enclosed space defined by the substrate, the film and the sealant. The contact sensor package further has at least a ground conductive trace formed on the substrate and an electrostatic charge dissipation layer formed on a surface of the film and electrically connected to the ground conductive trace. The electrostatic charge dissipation layer has an upper surface that serves as a contact surface for a detecting a contact work-piece.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: October 17, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Chang Lee, Cheng-Yin Lee, Yung-Li Lu, Ying-Tsai Yeh, Pei-Chi Lin
  • Publication number: 20060182120
    Abstract: Systems and methods for using VPLS to provide communications between IP devices connected to a provider service network (PSN) by a non-Ethernet access link and IP devices connected to a PSN by an Ethernet access link are described. In accordance with the systems and methods standard IP devices connected to existing and heterogeneous access technologies can communicate with each other as if they were connected to a common LAN segment. In particular the invention relates to the interworking of IP and VPLS.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 17, 2006
    Applicant: Alcatel
    Inventor: Cheng-Yin Lee
  • Publication number: 20060140190
    Abstract: A method and apparatus for configuring a communication path which traverses different network domains are provided. A set-up signal for configuring the communication path is generated and includes both an identifier for identifying one or more network resources in one network domain and a domain identifier associated with the resource identifier which identifies the resource(s) as belonging to that network domain. The domain identifier allows resource identifiers unique to one domain to be included in an inter-domain communication path set-up signal. An inter-domain set-up signal may include a group identifier for identifying resources of a primary path in place of a specific identification of each resource.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Applicant: ALCATEL
    Inventor: Cheng-Yin Lee
  • Publication number: 20060133265
    Abstract: Virtual private networking methods and systems are disclosed. A label switched path (LSP) is established between network elements which provide access to different autonomous systems (ASs). A record of resources which are used for the LSP is maintained, and a backup LSP is established between the network elements. The backup LSP excludes resources which were used for the LSP. Labeled routes associated with each AS are then redistributed to the network element within the other AS using the LSP or the backup LSP. In another embodiment, VPN labeled routes used by a first network element in a first AS and belonging to a VPN are aggregated into an aggregated inter-AS VPN labeled route, which is distributed to a second AS and redistributed to a second network element, in the second AS, which belongs to the VPN. A data structure for mapping VPN labeled routes to an aggregated inter-AS labeled route is also disclosed.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Inventor: Cheng-Yin Lee
  • Publication number: 20060130135
    Abstract: A method and system for connecting a customer equipment (CE) communication device to a virtual private network (VPN) is provided. A virtual private network membership signal is generated at the customer equipment and transmitted to service provider equipment. The signal includes an identifier which identifies the customer equipment as a member of the virtual private network. On receiving the signal, service provider equipment such as a network element verifies that the customer equipment belongs to the virtual private network based on the customer identifier and only connects the customer equipment to the VPN if the verification is successful. The membership signal may be generated by a customer identification device distributed to the customer and installed in customer equipment to be connected to a virtual private network.
    Type: Application
    Filed: December 10, 2004
    Publication date: June 15, 2006
    Inventors: Zlatko Krstulich, Cheng-Yin Lee