Patents by Inventor Cheng-Yu (Sean) Lin

Cheng-Yu (Sean) Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12235559
    Abstract: A double-layer cholesteric liquid crystal display and its manufacturing method are disclosed. The double-layer cholesteric liquid crystal display includes three transparent substrates, two opposing electrode layers, two cholesteric liquid crystal layers, and a first light-absorbing layer. Additionally, the double-layer cholesteric liquid crystal display incorporates two drive ICs and a second light-absorbing layer. The two drive ICs can be positioned either on the same side or on opposite sides within the non-display area of the double-layer cholesteric liquid crystal display. Furthermore, the first cholesteric liquid crystal layer exhibits a first color light, and the second cholesteric liquid crystal layer exhibits a second color light, where the colors are selected as contrasting colors. Additionally, the two cholesteric liquid crystal layers possess mutually opposite optical rotary properties.
    Type: Grant
    Filed: June 3, 2024
    Date of Patent: February 25, 2025
    Assignee: IRIS OPTRONICS CO., LTD.
    Inventors: Cheng-Yu Lin, Cheng-Hong Yao, Chi-Chang Liao
  • Publication number: 20250061727
    Abstract: The image recognition system includes an image sensor and an image processor. The image sensor acquires a plurality of sensed images of continuous frames. The image processor performs image recognition on the plurality of sensed images. The image processor determines on the plurality of sensed images respectively whether the sensed image is a valid frames not containing a road, to determine a plurality of valid sensed images. The image processor determines on the plurality of valid sensed images respectively whether a proportion of an area of a drivable area in a plurality of sub-image regions of the valid sensed image is less than a preset proportion, to perform danger marking. The image processor calculates the number of danger marks of the sub-image regions for each of the valid sensed images. When the number of danger marks is greater than a preset threshold, the image processor generates a danger warning.
    Type: Application
    Filed: November 29, 2023
    Publication date: February 20, 2025
    Inventors: Cheng Yu WEN, Yao-Ching PENG
  • Publication number: 20250057973
    Abstract: A drug carrier with a property of crossing the blood-brain barrier comprises an extracellular vesicle with a human leukocyte antigen-G antibody on its surface. This carrier can serve as a pharmaceutical composition for promoting apoptosis of brain tumor cells, inhibiting growth of brain tumor cells, or reducing expression of O6-methylguanine-DNA methyltransferase (MGMT) in brain tumor cells. These effects contribute to the treatment of glioblastoma multiforme (GBM).
    Type: Application
    Filed: August 13, 2024
    Publication date: February 20, 2025
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Yi-Wen Chen, Ming-You Shie, Chih-Ming Pan, Shi-Wei Huang, Yen Chen, Cheng-Yu Chen, Kai-Wen Kan
  • Patent number: 12228540
    Abstract: The present disclosure provides a biochemical test chip, including an insulating substrate, an electrode unit, a first insulating septum, a reactive layer and a second insulating septum. The electrode unit is located on the insulating substrate. The electrode unit includes a working electrode and a counter electrode. A current density of the counter electrode is greater than a current density of the working electrode. The first insulating septum is located on the electrode unit. The first insulating septum has an opening, which at least partially exposes the electrode unit. The reactive layer is located in the opening and is electrically connected to the electrode unit. The second insulating septum is located on the first insulating septum.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: February 18, 2025
    Assignee: APEX BIOTECHNOLOGY CORP.
    Inventors: Chen-Yu Yang, Cheng-Yu Chou
  • Publication number: 20250052982
    Abstract: An imaging lens system includes seven lens elements which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has negative refractive power. The image-side surface of the fifth lens element is convex in a paraxial region thereof. The sixth lens element has negative refractive power. The object-side surface of the sixth lens element is concave in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one of the seven lens elements has at least one inflection point.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 13, 2025
    Applicant: LARGAN INDUSTRIAL OPTICS CO., LTD.
    Inventors: Shiu Sheng LI, Cheng-Yu TSAI
  • Publication number: 20250050918
    Abstract: The present invention relates to a track-type robot, wherein at least one drive wheel is driven by a driving device disposed on a body to drive a running mechanism to travel on a track, so as to drive the track-type robot forward; when the track-type robot goes uphill or downhill, the running mechanism and the body perform relative deflection motions in forward and reverse directions through a pivoting element connecting the running mechanism with the body, in the forward and reverse axial rotating directions thereof, so the running mechanism and the drive wheel keep contact with the track when the track-type robot goes uphill and downhill.
    Type: Application
    Filed: August 6, 2024
    Publication date: February 13, 2025
    Inventors: HUNG-HIS LI, TSUNG-YEN LEE, CHENG-YU LEE, KUO-TSUNG HUANG
  • Patent number: 12222488
    Abstract: An observation carrier for a microscope is provided. The observation carrier includes a bottom base, an upper cover, and a chip. The upper cover is detachably disposed on the bottom base and has a window. The chip is integrated on the upper cover and includes a main body and a plurality of electrodes. The main body has an observation region, and the observation region corresponds to the window and is adapted to carry a sample material. The electrodes are disposed on the main body and are connected to the observation region.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 11, 2025
    Assignee: FlowVIEW Tek
    Inventors: Po-Yang Peng, Chun-Chieh Liang, Liang-Hsun Lai, Cheng-Yu Lee, Hsin-Hung Lee
  • Patent number: 12224574
    Abstract: Described are computer implemented methods, a system and a power supply amplifier (PSA) that supports compliance testing of the PSA. The power supplies power to a powered device/information handling system. A voltage of synchronous rectifier (SR) gate is measured and compared to a calculated sense voltage at a sense resistor of the PSA. If the sense voltage is zero, received current of the PSA bypasses a first blocking MOSFET and a second blocking MOSFET for over voltage protection. If the sense voltage is not zero, the received current passes through the first blocking MOSFET.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 11, 2025
    Assignee: Dell Products L.P.
    Inventors: Wei Cheng Yu, Merle Jackson Wood, III, Geroncio Ong Tan, Chi Che Wu
  • Publication number: 20250046702
    Abstract: A semiconductor structure includes an interconnect structure, a passivation structure, a first capacitor, and a contact feature. The interconnect structure is disposed over a semiconductor substrate. The passivation structure is disposed over the interconnect structure. The first capacitor is disposed within the passivation structure. The contact feature is disposed over the passivation structure, wherein the first capacitor is proximal to a corner of the contact feature. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: WEI-YU CHOU, YANG-CHE CHEN, TING-YUAN HUANG, TSE-WEI LIAO, CHENG-YU HSIEH, HSIANG-TAI LU
  • Publication number: 20250048693
    Abstract: A method of manufacturing a semiconductor device includes forming first and second active regions; forming first to fifth gate electrodes, the second gate electrode being between the first and third gate electrodes, the fourth gate electrode being between the third and fifth gate electrodes; and selectively replacing at least one portion of at least one of the gate electrodes with an isolation dummy gate, including: replacing the first and fifth gate electrodes with first and second isolation dummy gates formed in trenches through the first and second active regions; and replacing a first portion of the third gate electrode overlying the second active region with a third isolation dummy gate formed in a first trench through the second active region, resulting in a second portion of the third gate over the first active region, and the third isolation dummy gate aligned with the second portion of the third gate.
    Type: Application
    Filed: October 17, 2024
    Publication date: February 6, 2025
    Inventors: Cheng-Yu LIN, Yi-Lin FAN, Hui-Zhong ZHUANG, Sheng-Hsiung CHEN, Jerry Chang Jui KAO, Xiangdong CHEN
  • Publication number: 20250048703
    Abstract: Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 6, 2025
    Inventors: Cheng-Yu Wei, Hao-Ming Tang, Cheng-I Lin, Shu-Han Chen, Chi On Chui
  • Patent number: 12216359
    Abstract: A spliced reflective display includes multiple display devices, a front light guide plate, and at least one light source. Among the multiple display devices, one display device is joined side-by-side with another to form an adjacent joint. The front light guide plate is affixed above the multiple display devices and is close to the display side. It has a top surface near the display side and includes an optical structure. The at least one light source is positioned at the side of the front light guide plate, and light therefrom reflects off the top surface of the front light guide plate onto the multiple display devices, and the reflected light from the display devices forms image light that is directed towards the display side to produce an image. The optical structure directs the path of the image light to obscure the adjacent joint from being visible on the display side.
    Type: Grant
    Filed: June 3, 2024
    Date of Patent: February 4, 2025
    Assignee: IRIS OPTRONICS CO., LTD.
    Inventors: Cheng-Yu Lin, Cheng-Hong Yao, Chi-Chang Liao
  • Patent number: 12218129
    Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chen Ho, Hung Chih Hu, Hung Cheng Yu, Ju Ru Hsieh
  • Publication number: 20250036886
    Abstract: Using a large language model to comply with a user request. The large language model receives tool documentation for each of one or more tools, and analyzes the tool documentation for each of the one or more tools to determine, for each tool, one or more tasks that the tool is operable to perform. Upon receiving a request from a user, the large language model generates a plan for complying with the request by using one or more of the tools, the plan including performance of one or more of the tasks.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 30, 2025
    Inventors: Chen-Yu Lee, Alexander Ratner, Tomas Pfister, Chun-Liang Li, Yasuhisa Fujii, Ranjay Krishna, Cheng-Yu Hsieh, Si-An Chen
  • Publication number: 20250040096
    Abstract: An electronic device includes a shell element, at least one electronic element, a printed circuit board, and an anti-scalding mask. The shell element has an accommodating space and a metal surface. At least one electronic element is disposed in the accommodating space. The printed circuit board is disposed in the accommodating space and is electrically connected to the at least one electronic element. The anti-scalding mask covers and is disposed on the metal surface. The anti-scalding mask is made of a low thermal conductivity material, and a thermal conductivity of the low thermal conductivity material is less than or equal to 20 W/mK.
    Type: Application
    Filed: December 21, 2023
    Publication date: January 30, 2025
    Inventors: Yu-Fu KU, Cheng-Yu YEH
  • Patent number: 12211871
    Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20250026907
    Abstract: Additive-polymer precursor materials for filaments (e.g., for three-dimensional (3D) printing) are provided, as well as methods of fabricating and using the same. One or more two-dimensional (2D) additive materials (e.g., nano materials, such as nanosheets) can be mixed with a polymer base to give an additive-polymer precursor composite material. The additive material can be dissolved in a first solvent to give an additive solution, and the polymer can be dissolved in a second solvent to give a polymer base. The additive solution can be mixed with the polymer base to give a mixed solution. Solvent casting can then be performed on the mixed solution to evaporate the solvent(s) and give the additive-polymer precursor composite material, which can have a layered structure.
    Type: Application
    Filed: March 27, 2024
    Publication date: January 23, 2025
    Applicant: The Florida International University Board of Trustees
    Inventors: Daniela Rodica Radu, Cheng-Yu Lai, Melissa Venedicto, Faizan Syed, Dakota Aaron Thomas, Samuel Oyon
  • Publication number: 20250030012
    Abstract: A fuel cell interconnect includes fuel ribs disposed on a first side of the interconnect and a least partially defining fuel channels, and air ribs disposed on an opposing second side of the interconnect and at least partially defining air channels. The fuel channels include central fuel channels disposed in a central fuel field and peripheral fuel channels disposed in peripheral fuel fields disposed on opposing sides of the central fuel field. The air channels include central air channels disposed in a central air field and peripheral air channels disposed in peripheral air fields disposed on opposing sides of the central air field. At least one of the central fuel channels or the central air channels has at least one of a different cross-sectional area or length than at least one of the respective peripheral fuel channels or the respective peripheral air channels.
    Type: Application
    Filed: October 7, 2024
    Publication date: January 23, 2025
    Inventors: Michael D. GASDA, Cheng-Yu LIN, Ling-Hsiang CHEN, Harald HERCHEN, Ian RUSSELL, Tad ARMSTRONG
  • Publication number: 20250030236
    Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The weight average molecular weight of the second fluoropolymer ranges from 630000 g/mol to 1100000 g/mol. The conductive filler is dispersed in the polymer matrix, thereby forming an electrically conductive path in the heat-sensitive layer.
    Type: Application
    Filed: December 20, 2023
    Publication date: January 23, 2025
    Inventors: Hsiu-Che YEN, Chingting CHIU, Chia-Yuan LEE, Chen-Nan LIU, Cheng-Yu TUNG, Yung-Hsien CHANG, Yao-Te CHANG, Fu-Hua CHU
  • Publication number: 20250029755
    Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The first fluoropolymer has a first volume and a first melt flow index, and the second fluoropolymer has a second volume and a second melt flow index. The second melt flow index ranges from 0.4 g/10 min to 0.7 g/10 min and is lower than the first melt flow index, and a volume ratio by dividing the second volume by the first volume ranges from 0.4 to 0.6.
    Type: Application
    Filed: January 25, 2024
    Publication date: January 23, 2025
    Inventors: Chingting CHIU, Hsiu-Che YEN, Chia-Yuan LEE, Chen-Nan LIU, Cheng-Yu TUNG, Yung-Hsien CHANG, Yao-Te CHANG, Fu-Hua CHU