Abstract: The present invention provides a method to establish cloned game accounts, when an auction information is posted on the game account trading platform, the game account trading platform will establish a testing game interface according to the game interface under the relevant game account, and generate a cloned game account based on the game objects, so that the buyer user primary account can enter this testing game interface to test the cloned game account.

Abstract: A camera lifting structure includes a rail bracket, two fixing portions, two elastic elements, two sliding portions, two connecting rods and a camera module. The rail bracket extends along a first direction. The fixing portions are disposed on two ends of the rail bracket. The elastic elements locate between the fixing portions. Each elastic element has a first end and a second end. Each first end connects with the corresponding fixing portion. The sliding portions respectively connect with the corresponding second end and are configured to slide along the first direction relative to the rail bracket. Each connecting rod has a third end and a fourth end. Each third end is pivotally connected with the corresponding sliding portion. The camera module pivotally connects with the fourth ends and is configured to move relative to the rail bracket along a second direction perpendicular to the first direction.

Abstract: Disclosed are methods and devices of generating predicted brain images. The present disclosure provides a method of generating a predicted brain image. The method comprises: receiving a first brain image; encoding the first brain image to generate a latent vector; and decoding the latent vector and one or more conditional features to generate the predicted brain image. The first brain image is generated by a magnetic resonance imaging (MRI) method. The one or more conditional features include at least one of: an age in future, a gender, previous brain images, omics features, and medical history. The latent vector is multiplied by a first normal distribution.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate. An interconnect structure is disposed along a front-side surface of the substrate and comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second image sensor element is configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. The second image sensor element is laterally adjacent to the first image sensor element. Further, the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.

Abstract: Some embodiments relate to a CMOS image sensor disposed on a substrate. A plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions, and includes a first set of BDTI segments extending in a first direction and a second set of BDTI segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. The BDTI structure comprises a first material. A pixel deep trench isolation (PDTI) structure is disposed within the BDTI structure and overlies the photodiode. The PDTI structure comprises a second material that differs from the first material, and includes a first PDTI segment extending in the first direction such that the first PDTI segment is surrounded by the BDTI structure.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.

Abstract: Production of HFO-1132 and, in particular, HFO-1132E, may be produced from 1,1,2-trichloro-1,2,2-trifluoroethane (CFC-113). In a first step, 1,1,2-trifluoroethane (HFC-143) is produced by hydrogenating 1,1,2-trichloro-1,2,2-trifluoroethane (CFC-113) by reaction with hydrogen in the presence of a catalyst to produce 1,1,2-trifluoroethane (HFC-143). The 1,1,2-trifluoroethane (HFC-143) may then be dehydrofluorinated in the presence of a catalyst to produce trans-1,2-difluoroethylene (HFO-1132E) and/or cis-1,2-difluoroethylene (HFO-1132Z). The cis-1,2-difluoroethylene (HFO-1132Z) may then be isomerized to produce trans-1,2-difluoroethylene (HFO-1132E).

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface in a vertical direction, a first isolation structure disposed in the semiconductor substrate for defining pixel regions, a visible light detection structure, an infrared light detection structure, and a reflective layer. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region. The visible light detection structure includes a first portion disposed between the second surface and the infrared light detection structure in the vertical direction and a second portion disposed between the infrared light detection structure and the first isolation structure in a horizontal direction. The infrared light detection structure is disposed between the reflective layer and the first portion in the vertical direction. The second portion is not sandwiched between the reflective layer and the second surface in the vertical direction.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.

Abstract: A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer.

Abstract: A method for performing garbage collection (GC) management of a memory device with aid of block classification and associated apparatus are provided. The method may include: utilizing a memory controller to divide at least one portion of blocks among a plurality of blocks into multiple first blocks belonging to at least one first type in a first area and multiple second blocks belonging to at least one second type in a second area; utilizing the memory controller to receive a first command from a host device through a transmission interface circuit within the memory controller; and during writing data in response to the first command, performing a foreground GC procedure to control the memory device to perform GC before completing at least one writing operation corresponding to the first command, for controlling priority of releasing storage space of the second area to be higher than that of the first area.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

Abstract: A rack apparatus includes a mother rack including a rectangular platform member, a pivotal left L-shaped support, a pivotal right L-shaped support, a left groove on the platform member, a right groove on the platform member, and a space under the platform member; and a daughter rack including a rectangular platform element, a pivotal left leg, a pivotal right leg, a pivotal limit member disposed on a front end of the platform element, a pivotal surface disposed rearward of the pivotal limit member, a rear support leg having two ends pivotably secured to a back surface of the pivotal surface and the platform element respectively, and a space under the platform element. The left leg may be fastened in the left groove and the right leg may be fastened in the right groove respectively.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes at least one device on a front side of a semiconductor substrate. A plurality of grating layers are under the at least one device. The plurality of grating layers include at least a first material having a first refractive index alternating with a second material having a second refractive index. Contacts extend through an interlevel dielectric material, and further extend through the semiconductor substrate, to directly contact at least one of the first material and the second material below the at least one device and below the semiconductor substrate underlying the interlevel dielectric material.

Abstract: An electronic device is provided. The electronic device includes an antenna array including a plurality of antenna patterns collectively configured to provide a scan-angle coverage. Each of the antenna patterns includes a curved surface.

Abstract: A fuel cell interconnect includes fuel ribs disposed on a first side of the interconnect and a least partially defining fuel channels, and air ribs disposed on an opposing second side of the interconnect and at least partially defining air channels. The fuel channels include central fuel channels disposed in a central fuel field and peripheral fuel channels disposed in peripheral fuel fields disposed on opposing sides of the central fuel field. The air channels include central air channels disposed in a central air field and peripheral air channels disposed in peripheral air fields disposed on opposing sides of the central air field. At least one of the central fuel channels or the central air channels has at least one of a different cross-sectional area or length than at least one of the respective peripheral fuel channels or the respective peripheral air channels.

Abstract: A system for embedding credentials on an electronic document includes a task assignment device, a document database, a signature server and a credential server. The task assignment device generates an assigned task. The signature server generates a first signature request and a second signature request according to the assigned task. A first electronic device generates first signature information according to the first signature request. A second electronic device generates second signature information according to the second signature request. The signature server generates a first credential request and a second credential request according to the first signature information and the second signature information. The credential server transmits a first credential object and a second credential object to the signature server in response to the first credential request and the second credential request.

Abstract: A polymer, which is a composition of a battery, includes a polyester. The polyester is polymerized by at least two monomers, wherein each of the at least two monomers is selected from a group consisting of a carbonate ester and a polyol. The polyester can further include an end-capped polycarbonate ester, and the end-capped polycarbonate ester includes an inert group on an end thereof.