Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

Abstract: A memory structure includes a bottom via, a memory cell and a top via. The memory cell is disposed on the bottom via and includes a bottom electrode, a top electrode and a first storage element layer and a second storage element layer sandwiched between the bottom electrode and the top electrode. The first storage element layer is in contact with the bottom electrode, and a crystallization temperature of the first storage element layer is higher than a crystallization temperature of the second storage element layer. The top via is disposed on the memory cell and electrically connected to the top electrode.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.

Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body. A sidewall spacer is disposed on the sidewall of the conductive structure.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having an image sensor region arranged between sidewalls of the substrate that form one or more trenches. One or more dielectric materials are arranged along the sidewalls of the substrate that form the one or more trenches. A reflective region is disposed within the one or more trenches and laterally surrounded by the one or more dielectric materials. The reflective region includes a plurality of reflective portions that are arranged at different vertical positions within the reflective region and that have different reflective properties.

Abstract: Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.

Abstract: In some implementations described herein, a capacitor structure may include a metal-insulator-metal structure in which work function metal layers are included between the insulator layer of the capacitor structure and the conductive electrode layers of the capacitor structure. The work function metal layers may enable high-k dielectric materials to be used for the insulator layer in that the work function metal layers may provide an increased electron barrier height between the insulator layer and the conductive electrode layers, which may increase the breakdown voltage and may reduce the current leakage for the capacitor structure.