Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210050220
    Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.
    Type: Application
    Filed: October 14, 2020
    Publication date: February 18, 2021
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Patent number: 10923576
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee
  • Publication number: 20200411756
    Abstract: The present disclosure relates to a memory device. The memory device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate increases.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Patent number: 10879288
    Abstract: Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20200395281
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 10868013
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10867864
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung, Da-Yuan Lee
  • Patent number: 10868247
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai
  • Patent number: 10868136
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20200388756
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The structure also includes a resistance variable layer over the lower electrode and an ion diffusion barrier layer over the resistance variable layer. The structure further includes a capping layer over the ion diffusion barrier layer, and the capping layer is made of a metal material. In addition, the structure includes an upper electrode over the capping layer. The structure includes a protective element extending along a sidewall of the ion diffusion barrier layer and in direct contact with an interface between the resistance variable layer and the ion diffusion barrier layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hai-Dang TRINH, Hsing-Lien LIN, Cheng-Yuan TSAI
  • Patent number: 10854725
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function metal layer is performed, where the fluorine-based treatment removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the fluorine-based treatment, another metal layer is deposited over the treated work-function metal layer.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee
  • Publication number: 20200373357
    Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Publication number: 20200368264
    Abstract: The present invention provides an alcohol extract of Ajuga taiwanensis Nakai ex Murata exhibits significant effects on inhibiting the senescence in human WI-38 lung fibroblasts and human dermal fibroblasts. Moreover, the alcohol extract of A. taiwanensis is able to suppress the expression of the cofilin-1, a protein involved in actin dynamics and cell morphology and found to be increased in senescent cells. Suppression effect of cell senescence by this herb extract is more efficient in mild concentration without over-inhibition of cell viability and growth.
    Type: Application
    Filed: May 26, 2020
    Publication date: November 26, 2020
    Inventors: Yi-Jang Lee, Yun-Lian Lin, Chung-Sheng Huang, Cheng-Han Tsai, Chun-Yuan Chang, Bing-Ze Lin, Yuan-Heng Tu, Wei-Hsiang Hsu, Pin-Ho Lo
  • Patent number: 10824383
    Abstract: The present disclosure discloses a display device, which includes a casing, a plurality of proximity sensors, a communication module, a display screen, and a processing module. The proximity sensors are disposed with respect to the side walls of the casing, and the proximity sensors generate a position signal when other display device is close to the casing. The communication module is disposed in the casing, and the communication module is used for communicating with the other display device. The processing module electrically connects to the proximity sensors and the communication module. The processing module controls the display screen to show a particular frame according to the position signal, and the other display screen of the other display device to show the other particular frame via the communication module, wherein the particular frame is capable of being combined with the other particular frame to be an entire frame.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: November 3, 2020
    Assignee: Pegatron Corporation
    Inventors: Cheng-Wen Chang, Chen-Yu Tsai, Chun-Yuan Wang, Cheng-Yi Lee
  • Patent number: 10818857
    Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Wei Liang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Publication number: 20200335353
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends along sidewalls of the bottom electrode, the switching dielectric, and the top electrode and an upper surface of a lower dielectric layer. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The the sidewall spacer layer separates the lower etch stop layer from the lower dielectric layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Patent number: 10811600
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Publication number: 20200326827
    Abstract: A touch panel includes a first electrode layer and a second electrode layer. The first electrode layer has transmitting electrodes arranged in transmitting channels and traces respectively coupled to the transmitting channels. The second electrode layer has receiving electrodes arranged in receiving channels. At least one of the traces, the transmitting channels and one of the receiving channels in proximity of the traces form touch detection blocks that respectively correspond to the transmitting channels. For each touch detection block, in a circle area overlapped with at least one of the traces and substantially in the touch detection block corresponding to one of the transmitting channels, a summation of areas of the corresponded transmitting channel and the trace coupled to the corresponded transmitting channel is substantially larger than a summation of areas of the other transmitting channels and the other traces.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Inventors: Cheng-Hung TSAI, Chin-Yuan CHIANG, Wai-Pan WU, Shen-Feng TAI
  • Patent number: 10804071
    Abstract: An electron microscope specimen includes a first electron-transport layer, a second electron-transport layer, a spacer layer, and a carrier layer. The second electron-transport layer has a first opening, a second opening, and a viewing area, wherein the viewing area is between the first opening and the second opening. The spacer layer is sandwiched between the first electron-transport layer and the second electron-transport layer, and the spacer layer has an accommodating space communicating with the first opening and the second opening. The carrier layer is disposed on the second electron-transport layer, and has a viewing window, a first injection hole, and a second injection hole, wherein the viewing window is substantially aligned with the viewing area and the accommodating space, and the first injection hole and the second injection hole respectively communicate with the first opening and the second opening.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 13, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wen-Wei Wu, Wei-Huan Tsai, Jui-Yuan Chen, Cheng-Lun Hsin
  • Patent number: 10804464
    Abstract: A structure and formation method of a semiconductor device structure is provided. The method includes forming a lower electrode layer over a semiconductor substrate and forming a data storage layer over the lower electrode layer. The method also includes forming an ion diffusion barrier layer over the data storage layer and forming a capping layer over the ion diffusion barrier layer. The ion diffusion barrier layer is a metal material doped with nitrogen, carbon, or a combination thereof. The capping layer is made of a metal material. The method further includes forming an upper electrode layer over the capping layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Cheng-Yuan Tsai