Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12185640
    Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a memory cell over a substrate, where the memory cell comprises a data storage structure. A conductive interconnect is over the data storage structure and comprises a first protrusion adjacent to a first side of the data storage structure, where the first protrusion comprises a flat bottom surface. A spacer structure is disposed on the first side of the data storage structure. The spacer structure directly contacts the flat bottom surface of the first protrusion.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Patent number: 12183779
    Abstract: Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 12160995
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi-Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20240387578
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; two adjacent radiation-sensing regions formed in the substrate; and a trench isolation structure extending from the back surface of the substrate into the substrate between the two adjacent radiation-sensing regions. The trench isolation structure includes: a dielectric material; a first film being formed between the dielectric material and the substrate; a second film being formed between the first film and the dielectric material; and a third film being formed between the second film and the dielectric material. An electronegativity of the first film, an electronegativity of the second film and an electronegativity of the third film are different from each other.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: CHIH-YU LAI, MIN-YING TSAI, YEUR-LUEN TU, HAI-DANG TRINH, CHENG-YUAN TSAI
  • Publication number: 20240387299
    Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Sheng-Chan LI, Sheng-Chau CHEN, Cheng-Hsien CHOU, Cheng-Yuan TSAI
  • Publication number: 20240387148
    Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Che Wei Yang, Chih Cheng Shih, Sheng-Chan Li, Cheng-Yuan Tsai, Sheng-Chau Chen
  • Publication number: 20240379721
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Chan Li, Hau-Yi Hsiao, Che Wei Yang, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20240381793
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a bottom electrode over a substrate. A top electrode overlies the bottom electrode. A capping structure is disposed between the top electrode and the bottom electrode. The capping structure comprises a diffusion barrier layer vertically stacked with a metal layer. A switching structure is disposed between the bottom electrode and the capping structure. The switching structure comprises a dielectric layer on the bottom electrode and a first oxygen affinity layer on the dielectric layer. A first Gibbs free energy of the first oxygen affinity layer is less than a second Gibbs free energy of the dielectric layer. A first difference between the first Gibbs free energy and the second Gibbs free energy is less than ?100 kJ/mol.
    Type: Application
    Filed: January 29, 2024
    Publication date: November 14, 2024
    Inventors: Fa-Shen Jiang, Hai-Dang Trinh, Cheng-Yuan Tsai, Chung-Yi Yu
  • Publication number: 20240381663
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode structure and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20240371922
    Abstract: Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20240373760
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20240371685
    Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Yen-Liang Lin, Chia-Wen Zhong, Yao-Wen Chang, Min-Chang Ching, Kuo-Liang Lu, Cheng-Yuan Tsai, Ru-Liang Lee
  • Publication number: 20240363469
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20240363613
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Cheng-Hsien CHOU, Sheng-Chau CHEN, Cheng-Yuan TSAI
  • Publication number: 20240357835
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first interconnect dielectric layer over a substrate and surrounding a first interconnect. A second interconnect dielectric layer is over the first interconnect dielectric layer and surrounds at least a part of a second interconnect. A bottom electrode is over the substrate, a top electrode is over the bottom electrode, and a ferroelectric layer is between the bottom electrode and the top electrode. The ferroelectric layer includes a lower horizontally extending portion, an upper horizontally extending portion arranged above the lower horizontally extending portion, and a vertically extending portion coupling the lower horizontally extending portion and the upper horizontally extending portion. The vertically extending portion extends through the first interconnect dielectric layer and the second interconnect dielectric layer.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 12125763
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 12127483
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20240339422
    Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 10, 2024
    Inventors: Che Wei YANG, Kuo-Ming WU, Sheng-Chau CHEN, Cheng-Yuan TSAI, Hau-Yi HSIAO, Chung-Yi YU
  • Publication number: 20240332163
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Che Wei YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Publication number: 20240332026
    Abstract: A substrate grinding tool is configured to remove material from a semiconductor substrate in a grinding operation. In the grinding operation, the substrate grinding tool uses a combination of mechanical grinding and a chemical etchant to remove material from the semiconductor substrate. The chemical etchant may be heated to a high temperature, which may increase the etch rate of the chemical etchant. The use of the combination of mechanical grinding and the chemical etchant may increase the grinding rate of the substrate grinding tool for grinding semiconductor substrates, may reduce surface roughness for semiconductor substrates that are processed by the substrate grinding tool, and/or may reduce surface damage for semiconductor substrates that are processed by the substrate grinding tool, among other examples.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 3, 2024
    Inventors: Chi-Fan CHEN, Chun-Kai LAN, Zhen Yu GUAN, Hsun-Chung KUANG, Cheng-Yuan TSAI, Chung-Yi YU