Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230275064
    Abstract: Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 31, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11737280
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi-Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 11735635
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 11723212
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 11721794
    Abstract: A method for manufacturing reflective structure is provided. The method includes the operations as follows. A metallization structure is received. A plurality of conductive pads are formed over the metallization structure. A plurality of dielectric stacks are formed over the conductive pads, respectively, wherein the thicknesses of the dielectric stacks are different. The dielectric stacks are isolated by forming a plurality of trenches over a plurality of intervals between each two adjacent dielectric stacks.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Hua Lin, Yao-Wen Chang, Chii-Ming Wu, Cheng-Yuan Tsai, Eugene I-Chun Chen, Tzu-Chung Tsai
  • Patent number: 11715674
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 11716913
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Cheng-Yuan Tsai, Tzu-Chung Tsai, Fa-Shen Jiang
  • Patent number: 11705470
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Publication number: 20230207448
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 29, 2023
    Inventors: Paul YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Patent number: 11682652
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11683999
    Abstract: The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Publication number: 20230187294
    Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 15, 2023
    Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo, Ping-Tzu Chen, Cheng-Yuan Tsai
  • Patent number: 11670539
    Abstract: A method of making a semiconductor arrangement includes forming a first layer of molecular ions in a first wafer interface region of a first wafer, forming a second layer of molecular ions in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 11670584
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Ching-Chung Hsu, Chung-Long Chang
  • Patent number: 11664411
    Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, I-Nan Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 11665909
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
  • Publication number: 20230129760
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventors: Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Cheng-Hsien CHOU, Sheng-Chau CHEN, Cheng-Yuan TSAI
  • Patent number: 11637239
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
  • Publication number: 20230123774
    Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.
    Type: Application
    Filed: January 12, 2022
    Publication date: April 20, 2023
    Inventors: Hsing-Lien Lin, Jui-Lin Chu, Cheng-Yuan Tsai
  • Publication number: 20230103309
    Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang