Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a multi-layer, metal-containing film
    Patent number: 10176999
    Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai
  • Method for manufacturing multi-voltage devices using high-K-metal-gate (HKMG) technology
    Patent number: 10177043
    Abstract: A method for manufacturing multi-voltage devices is provided. The method includes forming a pair of logic gate stacks in a logic region of a semiconductor substrate and a pair of device gate stacks in a multi-voltage device region. The pair of logic gate stacks and the pair of device gate stacks include first dummy gate material. The pair of device gate stacks also includes a work function tuning layer. The method further includes depositing second dummy gate material over the pair of logic gate stacks. The first dummy gate material and the second dummy gate material from over a first logic gate stack of the pair of logic gate stacks are replaced with an n-type material. The first dummy gate material and the second dummy gate material from over a second logic gate stack of the pair of logic gate stacks are replaced with a p-type material.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han Tsao, Chii-Ming Wu, Cheng-Yuan Tsai, Yi-Huan Chen
  • RRAM cell bottom electrode formation
    Patent number: 10170699
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
  • Surface treatment and passivation for high electron mobility transistors
    Patent number: 10170579
    Abstract: A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band gap and a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap. The HEMT further includes a first oxide layer over the second III-V compound layer; a first interfacial layer over the first oxide layer; and a passivation layer over the first interfacial layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
  • SWITCHING LAYER SCHEME TO ENHANCE RRAM PERFORMANCE
    Publication number: 20180375022
    Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • MIM capacitor and method of forming the same
    Patent number: 10164003
    Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Switching layer scheme to enhance RRAM performance
    Patent number: 10164182
    Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Structure and method to expose memory cells with different sizes
    Patent number: 10163651
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Image device having multi-layered refractive layer on back surface
    Patent number: 10163949
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Semiconductor structure having integrated inductor therein
    Patent number: 10164001
    Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Che Lee, I-Nan Chen, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Getter, MEMS device and method of forming the same
    Patent number: 10155214
    Abstract: A getter is provided. The getter consists essentially of from about 0% to 50% of titanium, from about 0% to 50% zirconium, and from about 5% to 50% of tantalum. A MEMS device is provided. The MEMS device includes a substrate and a getter over the substrate. The getter consists essentially of from about 0% to 50% of titanium, from about 0% to 50% zirconium, and from about 5% to 50% of tantalum. A method of forming a MEMS device is provided. The method includes the following operations: providing a substrate; and providing a getter over the substrate, wherein the getter consists essentially of from about 0% to 50% of titanium, from about 0% to 50% zirconium, and from about 5% to 50% of tantalum, and wherein all of the percentages are atomic percentages.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Wei Liang, Cheng-Yuan Tsai, Chun-Wen Cheng, Chia-Shiung Tsai
  • SEMICONDUCTOR DEVICE, FILM STACK AND MANUFACTURING METHOD THEREOF
    Publication number: 20180337051
    Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Yao-Wen CHANG, Jian-Shiou HUANG, Cheng-Yuan TSAI
  • Stress monitoring device and method of manufacturing the same
    Patent number: 10134645
    Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai
  • Semiconductor device and method of manufacturing the same
    Patent number: 10115896
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Yao-Wen Chang, Cheng-Yuan Tsai, Chin-Wei Liang, Yen-Chang Chu
  • Image Sensors with Organic Photodiodes and Methods for Forming the Same
    Publication number: 20180308901
    Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
  • SIDEWALL PASSIVATION FOR HEMT DEVICES
    Publication number: 20180308953
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180301626
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: HAI-DANG TRINH, YAO-WEN CHANG, CHENG-YUAN TSAI, CHIN-WEI LIANG, YEN-CHANG CHU
  • Formation of getter layer for memory device
    Patent number: 10103078
    Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Chang, Cheng-Yuan Tsai, Kai-Wen Cheng
  • STRESS MINITORING DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180286769
    Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Inventors: CHEN-FA LU, CHENG-YUAN TSAI
  • Anti-reflective layer for backside illuminated CMOS image sensors
    Patent number: 10079257
    Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Yeur-Luen Tu, Cheng-Yuan Tsai, Cheng-Ta Wu, Chia-Shiung Tsai