Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure having integrated inductor therein
    Patent number: 10164001
    Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Che Lee, I-Nan Chen, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • MIM capacitor and method of forming the same
    Patent number: 10164003
    Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Image device having multi-layered refractive layer on back surface
    Patent number: 10163949
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Getter, MEMS device and method of forming the same
    Patent number: 10155214
    Abstract: A getter is provided. The getter consists essentially of from about 0% to 50% of titanium, from about 0% to 50% zirconium, and from about 5% to 50% of tantalum. A MEMS device is provided. The MEMS device includes a substrate and a getter over the substrate. The getter consists essentially of from about 0% to 50% of titanium, from about 0% to 50% zirconium, and from about 5% to 50% of tantalum. A method of forming a MEMS device is provided. The method includes the following operations: providing a substrate; and providing a getter over the substrate, wherein the getter consists essentially of from about 0% to 50% of titanium, from about 0% to 50% zirconium, and from about 5% to 50% of tantalum, and wherein all of the percentages are atomic percentages.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Wei Liang, Cheng-Yuan Tsai, Chun-Wen Cheng, Chia-Shiung Tsai
  • SEMICONDUCTOR DEVICE, FILM STACK AND MANUFACTURING METHOD THEREOF
    Publication number: 20180337051
    Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Yao-Wen CHANG, Jian-Shiou HUANG, Cheng-Yuan TSAI
  • Stress monitoring device and method of manufacturing the same
    Patent number: 10134645
    Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai
  • Semiconductor device and method of manufacturing the same
    Patent number: 10115896
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Yao-Wen Chang, Cheng-Yuan Tsai, Chin-Wei Liang, Yen-Chang Chu
  • Image Sensors with Organic Photodiodes and Methods for Forming the Same
    Publication number: 20180308901
    Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
  • SIDEWALL PASSIVATION FOR HEMT DEVICES
    Publication number: 20180308953
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180301626
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: HAI-DANG TRINH, YAO-WEN CHANG, CHENG-YUAN TSAI, CHIN-WEI LIANG, YEN-CHANG CHU
  • Formation of getter layer for memory device
    Patent number: 10103078
    Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Chang, Cheng-Yuan Tsai, Kai-Wen Cheng
  • STRESS MINITORING DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180286769
    Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Inventors: CHEN-FA LU, CHENG-YUAN TSAI
  • Anti-reflective layer for backside illuminated CMOS image sensors
    Patent number: 10079257
    Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Yeur-Luen Tu, Cheng-Yuan Tsai, Cheng-Ta Wu, Chia-Shiung Tsai
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180226501
    Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: HAN-CHIN CHIU, SHENG-DE LIU, YU-SYUAN LIN, YAO-CHUNG CHANG, CHENG-YUAN TSAI
  • Sidewall passivation for HEMT devices
    Patent number: 10020376
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Image sensors with organic photodiodes and methods for forming the same
    Patent number: 10008546
    Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20180158869
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 7, 2018
    Inventors: HARRY-HAK-LAY CHUANG, KUEI-HUNG SHEN, HSUN-CHUNG KUANG, CHENG-YUAN TSAI, RU-LIANG LEE
  • Magnetoresistive random access memory cell and fabricating the same
    Patent number: 9991440
    Abstract: The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a tunneling layer disposed over the pinned layer, a free layer disposed over the tunneling layer and a capping layer disposed over the free layer. The capping layer includes metal-oxide and metal-nitride materials.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Chia-Shiung Tsai, Cheng-Yuan Tsai, Kai-Wen Cheng
  • Film Scheme for Bumping
    Publication number: 20180151527
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Application
    Filed: September 21, 2017
    Publication date: May 31, 2018
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Resistive RAM structure and method of fabrication thereof
    Patent number: 9978938
    Abstract: A metal-insulator-metal (MIM) capacitor structure of an RRAM device includes a first electrode and a second electrode with an insulating layer interposing the first and second electrodes. The conductive filament providing for a switching function of the RRAM device may be formed within the insulating layer. Further, a nitrogen-rich metal layer interposes the second electrode and the insulating layer. The nitrogen-rich metal layer includes a greater nitrogen concentration than that of the adjacent second electrode.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin